IP Library Patent Application 13123180
Patent Application
App. No. 13/123,180

METHOD OF PRODUCING A SILICON-ON-SAPPHIRE TYPE HETEROSTRUCTURE

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Patent No.
US None
App. No.
13/123,180
Abstract

The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate onto a sapphire substrate and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate. In accordance with the method, grinding is carried out using a wheel with a grinding surface that comprises abrasive particles having a mean dimension of more than 6.7 μm; further, after grinding and before etching, the method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range of 150° C. to 170° C.

Claims (16)

1 . A method of producing a silicon-on-sapphire heterostructure comprising:

bonding a silicon-on-insulator substrate onto a sapphire substrate to form a bonded heterostructure; and

thinning the SOI substrate after forming the bonded heterostructure, comprising:

grinding the SOI substrate using a wheel with a grinding surface comprising abrasive particles having a mean dimension of more than 6.7 μm;

annealing the bonded heterostructure in a post-grinding annealing process at a maximum temperature in a range extending from 150° C. to 170° C. after grinding the SOI substrate; and

etching the SOI substrate after annealing the bonded heterostructure.

2 . The method of claim 1 , further comprising annealing the bonded heterostructure in a pre-grinding annealing process at a maximum temperature in a range extending from 150° C. to 180° C. prior to thinning the SOI substrate.

3 . The method of claim 2 , wherein an initial annealing temperature of the bonded heterostructure during the pre-grinding annealing process is less than 80° C.

4 . The method claim 3 , further comprising ramping up the temperature during the pre-grinding annealing process at a rate of about 1° C./min.

5 . The method of claim 1 , further comprising forming a layer of oxide on a bonding surface of the silicon-on-insulator substrate prior to bonding the silicon-on-insulator substrate onto the sapphire substrate.

6 . The method of claim 1 , further comprising activating a bonding surface of at least one of the silicon-on-insulator substrate and the sapphire substrate prior to bonding the silicon-on-insulator substrate onto the sapphire substrate.

7 . The method of claim 1 , wherein etching the SOI substrate comprising using a chemical etching solution in a wet chemical etching process.

8 . The method of claim 1 , wherein etching the SOI substrate comprises using reactive ion etching in a dry etching process.

9 . The method of claim 1 , wherein grinding the SOI substrate further comprises using a wheel with a grinding surface comprising abrasive particles having a mean dimension of 15 μm or more.

10 . The method of claim 9 , wherein grinding the SOI substrate further comprises using a wheel with a grinding surface comprising abrasive particles having a mean dimension of 31 μm or more.

11 . The method of claim 1 , wherein grinding the SOI substrate comprises applying a load to the wheel of 222.5 N or less.

Assignments (2)
CHANGE OF NAME Recorded Feb 28, 2012
From: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES; CHEMIN DES FRANQUES; PARC TECHNOLOGIES DES FONTAINES; BERNIN. FRANCE 38190
To: SOITEC
Reel/Frame 028138/0895 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2011
From: GAUDIN, GWELTAZ; VAUFREDAZ, ALEXANDRE; GUITTARD, FLEUR
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 026093/0367 →