Patent Assignment
Reel/Frame 028138/0895
Change of Name
Recorded: 2012-02-28
Pages: 22
Assignors
S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
Executed: 2011-09-06
CHEMIN DES FRANQUES
Executed: 2011-09-06
PARC TECHNOLOGIES DES FONTAINES
Executed: 2011-09-06
BERNIN. FRANCE 38190
Executed: 2011-09-06
Assignee
SOITEC
CHEMIN DES FRANGUES, PARC TECHNOLOGIQUE DES FONTAINES, BERNIN, 38190, FRANCE
Covered Properties
(52)
Process for Making a Gan Substrate
Process for the Transfer of a Thin Layer Formed in a Substrate with Vacancy Clusters
(110) Oriented Silicon Substrate and a Bonded Pair of Substrates Comprising Said (110) Oriented Silicon Substrate
Relaxation and Transfer of Strained Layers
Methods and Structures for Altering Strain in Iii-Nitride Materials
Methods of Forming Layers of Semiconductor Material Having Reduced Lattice Strain, Semiconductor Structures, Devices and Engineered Substrates Including Same
Improved Process for Preparing Cleaned Surfaces of Strained Silicon
Strain Engineered Composite Semiconductor Substrates and Methods of Forming Same
Epitaxial Methods and Structures for Forming Semiconductor Materials
Application:
12/610,092 →
Publication:
US 2010/0187568
Methods for Recycling Substrates and Fabricating Laminated Wafers
Semiconductor Structure Having a Protective Layer
Application:
12/678,978 →
Publication:
US 2010/0244203
Method for Transferring a Layer from a Donor Substrate Onto a Handle Substrate
Hybrid Semiconductor Substrate Including Semiconductor-on-Insulator Region and Method of Making the Same
Process for Manufacturing a Composite Substrate
Method for Treating Germanium Surfaces and Solutions to Be Employed Therein
Process of Treating Defects During the Bonding of Wafers
Systems and Methods for a Gas Treatment of a Number of Substrates
Application:
12/814,936 →
Publication:
US 2011/0305835
Methods and Structures for Bonding Elements
Methods of Forming Bonded Semiconductor Structures
Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region
Methods of Fabricating Multilayer Substrates
Substrate Having a Charged Zone in an Insulating Buried Layer
Methods of Forming Through Wafer Interconnects in Semiconductor Structures Using Sacrificial Material, and Semiconductor Structures Formed by Such Methods
Application:
12/879,637 →
Publication:
US 2012/0061794
Methods of Fabricating Semiconductor Structures and Devices Using Glass Bonding Layers, and Semiconductor Structures and Devices Formed by Such Methods
Thermalizing Gas Injectors for Generating Increased Precursor Gas, Material Deposition Systems Including Such Injectors, and Related Methods
Systems and Methods for Forming Semiconductor Materials by Atomic Layer Deposition
Formation of Substantially Pit Free Indium Gallium Nitride
Method of Initiating Molecular Bonding
Process for Manufacturing a Structure Comprising a Germanium Layer on a Substrate
Application:
12/937,920 →
Publication:
US 2011/0183493
Methods for Directly Bonding Together Semiconductor Structures, and Bonded Semiconductor Structures Formed Using Such Methods
Strain Relaxation Using Metal Materials and Related Structures
Metallic Carrier for Layer Transfer and Methods for Forming the Same
Iii-V Semiconductor Structures with Diminished Pit Defects and Methods for Forming the Same
Methods of Forming Iii/V Semiconductor Materials, and Semiconductor Structures Formed Using Such Methods
Patent:
8,148,252 →
Application:
13/038,920 →
Process for Fabricating a Multilayer Structure with Post-Grinding Trimming
Methods of Fabricating Semiconductor Structures or Devices Using Layers of Semiconductor Material Having Selected or Controlled Lattice Parameters
Iii-V Semiconductor Structures and Methods for Forming the Same
Methods for Bonding Semiconductor Structures Involving Annealing Processes, and Bonded Semiconductor Structures and Intermediate Structures Formed Using Such Methods
Methods of Forming Bonded Semiconductor Structures, and Semiconductor Structures Formed by Such Methods
Application:
13/077,292 →
Publication:
US 2012/0248621
Methods of Forming Bonded Semiconductor Structures Including Two or More Processed Semiconductor Structures Carried by a Common Substrate, and Semiconductor Structures Formed by Such Methods
Method of Producing a Silicon-on-Sapphire Type Heterostructure
Application:
13/123,180 →
Publication:
US 2011/0195560
Method to Fabricate and Treat a Structure of Semiconductor-on-Insulator Type, Enabling Displacement of Dislocations, and Corresponding Structure
Application:
13/126,376 →
Publication:
US 2011/0193201
Methods for Testing Semiconductor-on-Insulator Type Substrates
Application:
13/133,118 →
Publication:
US 2011/0233719
Method of Producing a Layer of Cavities
Method for Manufacturing Components
Adaptation of the Lattice Parameter of a Layer of Strained Material
Bonding Surfaces for Direct Bonding of Semiconductor Structures
Relaxation and Transfer of Strained Material Layers
Methods of Forming Bonded Semiconductor Structures Including Interconnect Layers Having One or More of Electrical, Optical, and Fluidic Interconnects Therein, and Bonded Semiconductor Structures Formed Using Such Methods
Methods of Forming Bonded Semiconductor Structures in 3D Integration Processes Using Recoverable Substrates, and Bonded Semiconductor Structures Formed by Such Methods
Methods of Forming Three Dimensionally Integrated Semiconductor Systems Including Photoactive Devices and Semiconductor-on-Insulator Substrates
Method of Fabricating a Multilayer Structure with Circuit Layer Transfer
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 23, 2009
From: FAURE, BRUCE
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
Reel/Frame 023557/0944 →
Assignment of Assignor's Interest
Dec 4, 2009
From: AULNETTE, CECILE; RADOUANE, KHALID
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
Reel/Frame 023609/0540 →
Assignment of Assignor's Interest
Dec 16, 2009
From: LETERTRE, FABRICE; BETHOUX, JEAN-MARC; BOUSSAGOL, ALICE
To: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
Reel/Frame 023664/0759 →
Assignment of Assignor's Interest
Feb 25, 2010
From: RADOUANE, KHALID; BALDARO, ALESSANDRO
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
Reel/Frame 023992/0336 →
Assignment of Assignor's Interest
Jan 18, 2012
From: ALLIBERT, FREDERIC; KERDILES, SEBASTIEN
To: SOITEC
Reel/Frame 027555/0082 →