METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

1 . A method of forming a bonded semiconductor structure, comprising:

providing a first semiconductor structure comprising at least one device structure;

bonding a second semiconductor structure to the first semiconductor structure at a temperature or temperatures below about 400° C.;

forming at least one through wafer interconnect through the second semiconductor structure and into the first semiconductor structure to the at least one device structure; and

bonding the second semiconductor structure on a side thereof opposite the first semiconductor structure to a third semiconductor structure.

2 . The method of claim 1 , wherein bonding the second semiconductor structure to the first semiconductor structure comprises:

bonding a relatively thicker semiconductor structure to the first semiconductor structure; and

thinning the relatively thicker semiconductor structure to form the second semiconductor structure, the second semiconductor structure comprising a relatively thinner portion of the relatively thicker semiconductor structure remaining bonded to the first semiconductor structure.

3 . The method of claim 2 , wherein thinning the relatively thicker semiconductor structure to form the second semiconductor structure comprises:

implanting ions into the relatively thicker semiconductor structure along an ion implant plane; and

fracturing the relatively thicker semiconductor structure along the ion implant plane.

4 . The method of claim 3 , wherein implanting ions into the relatively thicker semiconductor structure comprises implanting ions into the relatively thicker semiconductor structure prior to bonding the relatively thicker semiconductor structure to the first semiconductor structure.

5 . The method of claim 3 , wherein fracturing the relatively thicker semiconductor structure along the ion implant plane comprises fracturing the relatively thicker semiconductor structure along the ion implant plane after bonding the relatively thicker semiconductor structure to the first semiconductor structure.

6 . The method of claim 5 , wherein fracturing the relatively thicker semiconductor structure along the ion implant plane comprises heating the relatively thicker semiconductor structure to a temperature or temperatures below about 400° C. to cause the relatively thicker semiconductor structure to fracture along the ion implant plane.

7 . The method of claim 1 , further comprising selecting the second semiconductor structure to be at least substantially comprised of silicon.

8 . The method of claim 7 , further comprising selecting the second semiconductor structure to be at least substantially comprised of single crystal silicon.

9 . The method of claim 1 , further comprising forming the at least one through wafer interconnect through the second semiconductor structure and into the first semiconductor structure to the at least one device structure at a temperature or temperatures below about 400° C.

10 . The method of claim 1 , further comprising forming at least one heat management structure in the second semiconductor structure.

11 . The method of claim 10 , wherein forming at least one heat management structure comprises forming at least one dummy metal pad, electrically isolated from the at least one device structure in the first semiconductor structure.

12 . The method of claim 10 , further comprising tailoring a coefficient of thermal expansion of the second semiconductor structure by varying at least one of a size, a number, a composition, a location, and a shape of the at least one heat management structure.

13 . The method of claim 12 , further comprising tailoring the coefficient of thermal expansion of the second semiconductor structure such that a ratio of the coefficient of thermal expansion of the second semiconductor structure to a coefficient of thermal expansion of the first semiconductor structure is between 0.67 and 1.5.

14 . The method of claim 13 , further comprising tailoring the coefficient of thermal expansion of the second semiconductor structure such that the ratio is between 0.9 and 1.1.

15 . The method of claim 14 , further comprising tailoring the coefficient of thermal expansion of the second semiconductor structure to be at least substantially equal to a coefficient of thermal expansion of the first semiconductor structure.

16 . The method of claim 1 , further comprising bonding the second semiconductor structure to the third semiconductor structure at a temperature or temperatures below about 400° C.

17 . The method of claim 1 , further comprising forming additional device structures on the second semiconductor structure after bonding the second semiconductor structure to the first semiconductor structure and prior to bonding the second semiconductor structure to the third semiconductor structure.

18 . A method of forming a bonded semiconductor structure, comprising:

providing a first semiconductor structure comprising at least one device structure;

implanting ions into a second semiconductor structure and forming an ion implant plane within the second semiconductor structure

bonding the second semiconductor structure to the first semiconductor structure;

fracturing the second semiconductor structure along the ion implant plane, a portion of the second semiconductor structure remaining bonded to the first semiconductor structure;

forming at least one through wafer interconnect through the portion of the second semiconductor structure remaining bonded to the first semiconductor structure, into the first semiconductor structure, and to the at least one device structure; and

bonding the second semiconductor structure on a side thereof opposite the first semiconductor structure to a third semiconductor structure.

19 . The method of claim 18 , further comprising bonding the second semiconductor structure to the first semiconductor structure at a temperature or temperatures below about 400° C.

20 . The method of claim 18 , wherein fracturing the second semiconductor structure along the ion implant plane comprises heating the second semiconductor structure to a temperature or temperatures below about 400° C. to cause the second semiconductor structure to fracture along the ion implant plane.

21 . The method of claim 18 , further comprising forming the at least one through wafer interconnect at a temperature or temperatures below about 400° C.

22 . The method of claim 18 , further comprising forming at least one heat management structure comprising a dummy metal structure in the second semiconductor structure.

23 . The method of claim 18 , further comprising bonding the second semiconductor structure to the third semiconductor structure at a temperature or temperatures below about 400° C.

24 . The method of claim 18 , further comprising forming additional device structures on the second semiconductor structure after bonding the second semiconductor structure to the first semiconductor structure and prior to bonding the second semiconductor structure to the third semiconductor structure.

25 . The method of claim 24 , further comprising forming the additional device structures on the second semiconductor structure without exposing the first semiconductor structure and the second semiconductor structure to any temperature over about 400° C.

26 . The method of claim 18 , further comprising selecting the second semiconductor structure to be at least substantially comprised of silicon.

27 . The method of claim 26 , further comprising selecting the second semiconductor structure to be at least substantially comprised of single crystal silicon.

28 . A bonded semiconductor structure, comprising:

a first semiconductor structure comprising at least one device structure;

a second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure comprising a portion of a fractured relatively thicker semiconductor structure; and

at least one through wafer interconnect extending through the second semiconductor structure, at least partially through the first semiconductor structure, and to the at least one device structure.

29 . The semiconductor structure of claim 28 , further comprising at least one heat management structure in the second semiconductor structure.

30 . The semiconductor structure of claim 28 , further comprising a third semiconductor structure bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure.

31 . The semiconductor structure of claim 28 , wherein the second semiconductor structure has a coefficient of thermal expansion at least substantially equal to a coefficient of thermal expansion of the first semiconductor structure.

32 . The semiconductor structure of claim 28 , wherein the second semiconductor structure is at least substantially comprised of silicon.

33 . The semiconductor structure of claim 32 , wherein the second semiconductor structure is at least substantially comprised of single crystal silicon.