Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods

1. A method of forming a semiconductor device, comprising:

providing a substrate, the substrate comprising a layer of semiconductor material on a layer of electrically insulating material;

forming a first metallization layer comprising a plurality of electrically conductive features on the substrate over a first side of the layer of semiconductor material opposite the layer of electrically insulating material;

forming a plurality of through wafer interconnects at least partially through the substrate, and forming at least one through wafer interconnect of the plurality of through wafer interconnects to extend through each of the first metallization layer and the layer of semiconductor material;

forming a second metallization layer comprising a plurality of electrically conductive features over a second side of the layer of semiconductor material opposite the first side of the layer of semiconductor material; and

providing an electrical pathway extending continuously through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material.

2. The method of claim 1 , wherein providing the substrate comprises selecting the substrate to comprise a semiconductor-on-insulator (SeOI) substrate.

3. The method of claim 2 , wherein selecting the substrate to comprise a semiconductor-on-insulator (SeOI) substrate comprises selecting the substrate to comprise a silicon-on-insulator (SOI) substrate.

4. The method of claim 2 , wherein the layer of semiconductor material has an average total thickness of about one micron or less, and wherein the layer of electrically insulating material comprises a layer of oxide material having an average total thickness of about one 300 nm or less.

5. The method of claim 1 , wherein forming the at least one through wafer interconnect of the plurality of through wafer interconnects to extend through each of the metallization layer and the layer of semiconductor material further comprises forming the at least one through wafer interconnect of the plurality of through wafer interconnects to extend through the layer of electrically insulating material.

6. The method of claim 1 , further comprising bonding at least one of the first processed semiconductor structure and the second processed semiconductor structure to the substrate over the first side of the layer of semiconductor material.

7. The method of claim 6 , wherein bonding at least one of the first processed semiconductor structure and the second processed semiconductor structure to the substrate over the first side of the layer of semiconductor material comprises directly bonding the at least one of the first processed semiconductor structure and the second processed semiconductor structure to the substrate in a metal-to-metal direct bonding process at a temperature or temperatures below about 400° C.

8. The method of claim 1 , further comprising forming at least one of the first processed semiconductor structure and the second processed semiconductor structure in situ on the substrate over the first side of the layer of semiconductor material.

9. The method of claim 1 , wherein providing an electrical pathway further comprises configuring the electrical pathway to extend through at least one conductive feature of the first metallization layer, through the at least one through wafer interconnect of the plurality of through wafer interconnects extending through each of the first metallization layer and the layer of semiconductor material, through at least one conductive feature of the second metallization layer, and through at least another through wafer interconnect of the plurality of through wafer interconnects.

10. The method of claim 1 , further comprising structurally and electrically connecting at least one conductive feature of the second metallization layer to a conductive feature of another substrate.

11. The method of claim 1 , further comprising individually selecting each of the first processed semiconductor structure and the second processed semiconductor structure from the group consisting of an electronic signal processor device, an electronic memory device, an electromagnetic radiation emitter device, and an electromagnetic radiation receiver device.

12. The method of claim 11 , further comprising:

selecting the first processed semiconductor structure to comprise an electronic signal processor device; and

selecting the second processed semiconductor structure to comprise at least one of an electronic memory device, a light-emitting diode, a laser-emitting diode, and a solar cell.