Real-time data pattern analysis system and method of operation thereof

1. A method comprising:

storing a plurality of senones in a memory module;

transferring the plurality of senones from the memory module to an integrated data transfer module at 256 bits per transfer and greater;

transferring the plurality of senones from the integrated data transfer module to the computational unit;

comparing processed data to the plurality of senones using the computational unit to generate one or more senone scores, wherein the memory module, integrated data transfer module, and computational unit are integrated on the same integrated circuit, and wherein the processed data is received by the integrated circuit from an external source; and

transferring the one or more senone scores off-chip from the integrated circuit.

2. The method of claim 1 , further comprising:

converting a data stream into the processed data using a signal processing module.

3. The method of claim 1 , wherein the comparing the processed data to the plurality of senones using the computational unit comprises generating a senone score output from the computational unit.

4. The method of claim 3 , wherein the generating comprises calculating a multivariate Gaussian probability for the plurality of senones.

5. The method of claim 1 , wherein the transferring the plurality of senones from the memory module to the integrated data transfer module comprises receiving the plurality of senones at a data transfer rate exceeding 1 gigabyte per second.

6. The method of claim 1 , further comprising:

controlling an external interface to the integrated circuit with a microcontroller state machine module.

7. The method of claim 1 , wherein the transferring the plurality of senones from the memory module to the integrated data transfer module comprises transferring the plurality of senones from the memory module to the integrated data transfer module at greater than 256 bits, per transfer.

8. A system comprising:

a memory module configured to store a plurality of senones;

a computational unit configured to compare processed data to the plurality of senones; and

an integrated data transfer module configured to receive the plurality of senones from the memory module at 256 bits per transfer and greater and to transfer the plurality of senones to the computational unit to generate one or more senone scores, wherein the memory module, integrated data transfer module, and computational unit are integrated on the same integrated circuit, wherein the processed data is received by the integrated circuit from an external source, and wherein the one or more senone scores are transferred off-chip from the integrated circuit.

9. The system of claim 8 , wherein the memory module comprises a non-volatile memory core.

10. The system of claim 8 further comprising:

a microcontroller state machine module configured to control an external interface.

11. The system of claim 8 , wherein the integrated data transfer module comprises a high-bandwidth massively parallel data bus, a memory buffer, and a high-bandwidth data bus.

12. The system of claim 8 , further comprising:

a signal processing module configured to convert a data stream into the processed data.

13. The system of claim 8 , wherein the computational unit is configured to calculate a senone score output.

14. The system of claim 13 , wherein the senone score output is based on a multivariate Gaussian probability for the plurality of senones.

15. The system of claim 8 , wherein the integrated data transfer module is configured to receive the plurality of senones at a data transfer rate exceeding 1 gigabyte per second.

16. The system of claim 8 , wherein the integrated data transfer module is configured to receive the plurality of senones from the memory module at greater than 256 bits per transfer.