Semiconductor device and test method thereof
View Patent ↗A semiconductor device includes a plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies an enable signal to the plurality of core chips through the first current path, and the plurality of core chips are activated based on a logic level of a bit corresponding to the chip identification information among a plurality of bits configuring the enable signal. The present invention can reduce the number of through silicon vias required to supply an enable signal.
1. A semiconductor device comprising:
a plurality of core chips each of which comprises a memory cell array including a plurality of memory cells; and
an interface chip that controls the core chips, wherein
the interface chip and the core chips are stacked,
the core chips are electrically connected in common to the interface chip through a first current path,
the interface chip serially supplies an enable signal comprised of a plurality of bits to the core chips through the first current path, each of the bits of the enable signal being assigned to an associated one of the core chips, and
each of the core chips is activated based on a logic level of an associated one of the bits of the enable signal.
2. The semiconductor device as claimed in claim 1 , wherein
the core chips are electrically connected in common to the interface chip through a second current path,
the interface chip supplies a timing signal synchronized with the enable signal to the core chips through the second current path, and
the core chips take in the enable signal in synchronization with the timing signal.
3. The semiconductor device as claimed in claim 1 , wherein
the core chips are electrically connected in common to the interface chip through a third current path,
the interface chip serially supplies a disable signal comprised of a plurality of bits to the core chips through the third current path, each of the bits of the disable signal being assigned to an associated one of the core chips, and
each of core chips is deactivated based on a logic level of an associated one of the bit of the disable signal.
4. The semiconductor device as claimed in claim 3 , wherein each of core chips is deactivated based on the logic level of the associated one of the bit of the disable signal irrespectively of the enable signal.
5. The semiconductor device as claimed in claim 1 , wherein
each of the core chips is electrically connected to the interface chip through an associated one of fourth current paths,
each of the core chips generates a layer test result signal by compressing test data read from the memory cell array when activated based on the enable signal, and
each of the core chips further comprise a first test circuit which supplies the layer test result signal to the interface chip through the associated one of the fourth current paths.
6. The semiconductor device as claimed in claim 5 , wherein the interface chip comprises a second test circuit that outputs the layer test result signals supplied from the core chips to outside.
7. The semiconductor device as claimed in claim 6 , wherein
each of the core chips includes at least a same number of through silicon vias as a number of the core chips,
each of the through silicon vias is electrically connected to one of the through silicon vias included in adjacent one of the core chips arranged in a different plane position viewed from a stacking direction, and
each of the fourth current paths is configured by the through silicon vias electrically connected.
8. The semiconductor device as claimed in claim 7 , wherein each of the first test circuits outputs the layer test result signal to one of the through silicon vias arranged in a same plane position viewed from the stacking direction.
9. A semiconductor device comprising:
a plurality of core chips each of which comprises a memory cell array including a plurality of memory cells, and to which chip identification information different from each other are allocated; and
an interface chip which controls the core chips, wherein
the interface chip and the core chips are stacked,
the core chips are electrically connected in common to the interface chip through a first current path,
each of the core chips is electrically connected to the interface chip through an associated one of fourth current paths,
the interface chip supplies an enable signal to the core chips through the first current path,
the core chips are selectively activated by comparing the enable signal and the chip identification information, and
each of the core chips is activated according to the enable signal, activated one of the core chips generating a layer test result signal by compressing test data read from the memory cell array and supplies the layer test result signal to the interface chip through the associated one of the fourth current paths.
10. The semiconductor device as claimed in claim 9 , wherein
the core chips are electrically connected in common to the interface chip through a second current path,
the interface chip supplies a timing signal synchronized with the enable signal to the core chips through the second current path, and
the core chips take in the enable signal in synchronization with the timing signal.
11. The semiconductor device as claimed in claim 9 , wherein
the core chips are electrically connected in common to the interface chip through a third current path,
the interface chip supplies a disable signal to the core chips through the third current path, and
each of the core chips is deactivated according to the disable signal, disable one of the core chips does not read the test data from the memory cell array.
12. A method of testing a semiconductor device comprising:
providing the semiconductor device including a plurality of core chips each of which comprises a memory cell array including a plurality of memory cells and an interface chip that controls the core chips, the interface chip and the plurality of core chips being stacked;
serially supplying an enable signal comprised of a plurality of bits from the interface chip to the core chips through a first current path electrically connected in common to the core chips, each of the bits of the enable signal being assigned to an associated one of the core chips;
activating one or more of core chips based on a logic level of each bit of the enable signal;
generating a layer test result signal by compressing test data read from the memory cell array in activated one or more of the core chips; and
supplying the layer test result signal from activated one or more of the core chips to the interface chip through an associated one of fourth current paths.