A first switch is arranged such that a first terminal thereof is connected to an AC test unit and a second terminal thereof is connected to an I/O terminal and a DC test unit. A first switch is configured so as to be capable of switching states between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A bypass capacitor is arranged between the first terminal and the second terminal, and is configured to bypass the frequency component which is cut off by the first switch.
1. A pin card comprising:
an input/output terminal to be connected to a device under test;
an optical semiconductor switch arranged such that a first terminal thereof is connected to an AC test unit configured to perform an AC test operation for the device under test and a second terminal thereof is connected to the input/output terminal and a DC test unit configured to perform a DC test operation for the device under test, and configured to be capable of switching states, between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which the first terminal and the second terminal are disconnected from each another;
a bypass capacitor arranged between the first terminal and the second terminal, and arranged as an external component of the optical semiconductor switch;
a first inductor arranged between the first terminal of the optical semiconductor switch and one terminal of the bypass capacitor; and
a second inductor arranged between the second terminal of the optical semiconductor switch and the other terminal of the bypass capacitor.
2. The pin card according to claim 1 , wherein the capacitance of the bypass capacitor is set in a range between 2 pF and 10 μF.
3. The pin card according to claim 1 , further comprising:
a first resistor arranged in parallel with the first inductor; and
a second resistor arranged in parallel with the second inductor.
4. The pin card according to claim 1 , wherein the capacitance of the bypass capacitor is set in a range between 1 pF and 10 μF.
5. The pin card according to claim 1 , further comprising a pre-emphasis resistor arranged in series with the bypass capacitor.
6. The pin card according to claim 1 , further comprising a pre-emphasis resistor and a capacitor arranged in series so as to form a path in parallel with the bypass capacitor.
7. The pin card according to claim 1 , wherein the bypass capacitor is formed using a pattern on, or otherwise a pattern in, a substrate on which the optical semiconductor switch is mounted.
8. A test apparatus comprising a pin card according to claim 1 .
9. A test apparatus comprising:
an input/output terminal to be connected to a device under test;
an AC test unit configured to perform an AC test operation for the device under test;
a DC test unit configured to perform a DC test operation for the device under test;
an optical semiconductor switch arranged such that a first terminal thereof is connected to the AC test unit and a second terminal thereof is connected to the input/output terminal, and configured to be capable of switching states, between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which the first terminal and the second terminal are disconnected from each another;
a bypass capacitor arranged between the first terminal and the second terminal, and arranged as an external component of the optical semiconductor switch;
a first inductor arranged between the first terminal of the optical semiconductor switch and one terminal of the bypass capacitor; and
a second inductor arranged between the second terminal of the optical semiconductor switch and the other terminal of the bypass capacitor.
10. The pin card according to claim 1 , wherein, in the DC test operation, the optical semiconductor switch is set to the disconnection state, and the AC test unit is set to a silent state.
11. The test apparatus according to claim 9 , wherein, in the DC test operation, the optical semiconductor switch is set to the disconnection state, and the AC test unit is set to a silent state.
12. The test apparatus according to claim 9 , wherein the capacitance of the bypass capacitor is set in a range between 2 pF and 10 μF.
13. The test apparatus according to claim 9 , further comprising:
a first resistor arranged in parallel with the first inductor; and
a second resistor arranged in parallel with the second inductor.
14. The test apparatus according to claim 9 , wherein the capacitance of the bypass capacitor is set in a range between 1 pF and 10 μF.
15. The test apparatus according to claim 9 , further comprising a pre-emphasis resistor arranged in series with the bypass capacitor.
16. The test apparatus according to claim 9 , further comprising a pre-emphasis resistor and a capacitor arranged in series so as to form a path in parallel with the bypass capacitor.
17. The test apparatus according to claim 9 , wherein the bypass capacitor is formed using a pattern on, or otherwise a pattern in, a substrate on which the optical semiconductor switch is mounted.