Cryptography circuit protected against observation attacks, in particular of a high order
A cryptography circuit protected against observation attacks comprises at least one register R providing a variable x masked by the mask m, the masked variable being encrypted by a first substitution box S -in a cyclic manner. The circuit also comprises a mask register M delivering at each cycle a mask m t , the transformation of m, the mask m being extracted from m t before being encrypted by a second substitution box S′, the new mask m′ obtained on output from this box S′ is transformed into a mask m′ t before being stored in the mask register M. The transformation consists of a bijection or a composition law making it possible to reduce or indeed to cancel any high-order attack in accordance with a model of activity of the registers R and M. Cryptography circuits are protected against high-order observation attacks on installations based on masking.
1. A cryptography circuit comprising:
at least one register R providing a variable x masked by a mask variable m , said masked variable being encrypted by a first substitution box S in a cyclic manner, and
a mask register M delivering at each cycle a transformed mask m t equal to the mask m transformed by a modification function, the mask m being encrypted by a second substitution box S′, a new mask m′ obtained on output from the second substitution box S′ being used to mask the variable,
wherein the modification is a bijection B such that the transformed mask m t is stored in the register M, the mask m applied to the substitution box being equal to B(m t ) and a new value to be stored in a register being B −1 (m′), m′ being the output from the second substitution box S′.
2. The circuit according to claim 1 , wherein the new transformed mask m′ t is introduced into the mask register M after having been subjected to the modification inverse to said modification function on output from the second substitution box S′.
3. The circuit according to claim 1 , wherein the bijection B is such that a Hamming weight of the mask m is one of identical and not identical to a Hamming weight of its image under the bijection B(m).
4. The circuit according to claim 1 , further comprising an encipherment algorithm of a DES type, a path of the data x, m is split into two parts, left and right, said circuit comprises in addition to a left mask register ML and a right mask register MR a third mask register M, the register MR containing a right sub-mask m r1 and the register ML containing a left sub-mask m l2 , the register M containing a sub-mask m r2 equal to a sub-mask m l1 , effective values of a right mask m r and of a left mask m l being such that:
m r =m r1 θ m r2
m l =m l1 θ m l2.
5. The circuit according to claim 1 , wherein the second substitution box S′ comprises two boxes identical to the first substitution box S and two XOR gates, the outputs of the two boxes being connected to an XOR gate whose output delivers the new mask m′, the masked variable (x ⊕ m) entering a box and on the other XOR gate whose other input receives the mask m, the output of this gate entering the other box.
6. The circuit according to claim 5 , wherein a ROM memory carries out the logic of the XOR gates and the substitution of the boxes.
7. A cryptography circuit comprising:
at least one register R providing a variable x masked by a mask variable m, said masked variable being encrypted by a first substitution box S in a cyclic manner, and
a mask register M delivering at each cycle a transformed mask m t equal to the mask m transformed by a modification function, the mask m being encrypted by a second substitution box S′, a new mask m′ obtained on output from the second substitution box S′ being used to mask the variable,
wherein the modification of the mask m is performed by decomposition into two sub-masks m 1 and m 2 such that m=m 1 θ m 2 where θ is a group composition law, the first sub-mask m 1 being stored in a first mask register M 1 and the second sub-mask m 2 being stored in a second mask register M 2 , a new value to be stored in the register M 1 being m′ 1 =m′ θ −1 m′ 2 and the new value to be stored being m′ 2 , m′ being a value of the mask on output from the second substitution box S′.
8. The circuit according to claim 7 , wherein the composition law is the XOR “exclusive or” operation.
9. The circuit according to claim 7 , wherein the composition law is the addition operation.
10. The circuit according to claim 7 , wherein the composition law is the multiplication operation.
11. The circuit according to claim 7 , wherein the composition law is the operation of the type s=a*b+(a+b)/2, * being multiplication and + being addition.
12. The circuit according to claim 7 , wherein the composition law has a Hamming distance between two consecutive sub-masks m 2 from one cycle to another, Δm 2 , that is non-zero.
13. The circuit according to claim 12 , wherein the sub-masks m 1 , m 2 having an even number of bits, the group composition law (α) making it possible to obtain the mask m on the basis of the sub-masks m 1 , m 2 satisfies:
Δm 2 =1 per groups of 2 bits;
m=m 1 ⊕ m 2 if m 2 MSB=1 or m=m 1 if m 2 MSB=0
m 2 MSB, m 2 LSB being respectively the high-order and low-order bits of the sub-mask m 2 .
14. The circuit according to claim 7 , further comprising:
a random-values generator, said generator delivering the value of the second sub-mask m′ 2 .
15. The circuit according to claim 5 , wherein the sub-mask m 1 arising from the first mask register M 1 is saved in the second mask register M 2 at the end of the cycle, the first register M 1 receiving for its part the new mask m′ 1 so as to reconstruct the new complete mask m′=m′ 1 θ m′ 2 .