Ternary content addressable memory cell having single transistor pull-down stack

1. A ternary content addressable memory (CAM) cell for comparing a comparand bit with a data value having one of three possible states represented by a data bit and a mask bit, the CAM cell comprising:

a data cell to store the data bit;

a mask cell to store the mask bit; and

a compare circuit coupled to the data cell and the mask cell, and including a discharge path between a match line and ground potential, wherein the discharge path consists essentially of a single transistor, wherein:

the single transistor is a first match line pull-down transistor connected between the match line and ground potential, and having a gate responsive to a logical combination of the data bit, the mask bit, and the comparand bit; and

the compare circuit further comprises a second match line pull-down transistor connected between the match line and ground potential, and having a gate responsive to a logical combination of a complemented data bit, the mask bit, and a complemented comparand bit.

2. The CAM cell of claim 1 , wherein the compare circuit further comprises:

first and second pass transistors connected in series between the data cell and the gate of the first match line pull-down transistor, the first pass transistor having a gate to receive the mask hit, and the second pass transistor having a gate to receive the comparand bit.

3. The CAM cell of claim 2 , wherein the compare circuit further comprises:

third and fourth pass transistors connected in series between the data cell and the gate of the second match line pull-down transistor, the third pass transistor having a gate to receive the mask bit, and the fourth pass transistor having a gate to receive the complemented comparand bit.

4. The CAM cell of claim 3 , wherein the pass transistors are PMOS transistors.

5. The CAM cell of claim 2 , wherein the compare circuit further comprises:

first and second gating transistors connected in parallel between the gate of the first match line pull-down transistor and ground potential, the first gating transistor having a gate to receive the mask bit, and the second gating transistor having a gate to receive the comparand bit.

6. The CAM cell of claim 5 , wherein the compare circuit further comprises:

third and fourth gating transistors connected in parallel between the gate of the second match line pull-down transistor and ground potential, the third gating transistor having a gate to receive the mask bit, and the fourth gating transistor having a gate to receive the complemented comparand bit.

7. The CAM cell of claim 6 , wherein the gating transistors are NMOS transistors.

8. A ternary content addressable memory (CAM) cell for comparing a comparand bit with a data value having one of three possible states represented by a data bit and a mask bit, the CAM cell comprising:

a data cell to store the data bit;

a mask cell to store the mask bit; and

a compare circuit coupled to the data cell and the mask cell, and including a discharge path between a match line and ground potential, wherein the discharge path consists essentially of a single transistor, wherein:

the single transistor is a match line pull-down transistor connected between the match line and ground potential, and having a gate that is responsive to a first logical combination of the data bit, the mask bit, and a complemented comparand bit, and that is responsive to a second logical combination of a complemented data bit, a complemented mask bit, and the comparand bit.

9. The CAM cell of claim 8 , wherein the compare circuit further comprises:

a first pass transistor connected between the data cell and a first node, and having a gate to receive the comparand bit; a first gating transistor connected between the first node and ground potential, and having a gate to receive the comparand bit; and

a first control transistor connected between the first node and the gate of the match line pull-down transistor, and Laving a gate to receive the complemented mask bit.

10. The CAM cell of claim 9 , wherein the compare circuit further comprises:

a second pass transistor connected between the data cell and a second node, and having a gate to receive the complemented comparand bit; a second gating transistor connected between the second node and ground potential, and having a gate to receive the complemented comparand bit; and

a second control transistor connected between the second node and the gate of the match line pull-down transistor, and having a gate to receive the mask bit.

11. The CAM cell of claim 10 , wherein the pass transistors are PMOS transistors.

12. The CAM cell of claim 10 , wherein the control transistors are PMOS transistors.

13. The CAM cell of claim 10 , wherein the gating transistors are NMOS transistors.

14. The CAM cell of claim 10 , wherein the pass transistors and the control transistors are NMOS transistors.

15. A ternary content addressable memory (CAM) cell for comparing a comparand bit with a data value having one of three possible states represented by a data bit and a mask bit, the CAM cell comprising:

a data cell to store the data bit;

a mask cell to store the mask bit; and

a compare circuit coupled to the data cell, the mask cell, and a match line, the compare circuit comprising:

a first match line pull-down transistor connected between the match line and ground potential, and having a gate that is responsive to a logical combination of the data bit, the mask bit, and the comparand bit; and

a second match line pull-down transistor connected between the match line and ground potential, and having a gate that is responsive to a logical combination of a complemented data bit, the mask bit, and a complemented comparand bit.

16. The CAM cell of claim 15 , wherein the compare circuit further comprises:

first and second pass transistors connected in series between the data cell and the gate of the first match line pull-down transistor, the first pass transistor having a gate to receive the mask bit, and the second pass transistor having a gate to receive the comparand bit.

17. The CAM cell of claim 16 , wherein the compare circuit further comprises:

third and fourth pass transistors connected in series between the data cell and the gate of the second match line pull-down transistor, the third pass transistor having a gate to receive the mask bit, and the fourth pass transistor having a gate to receive the complemented comparand bit.

18. The CAM cell of claim 17 , wherein the pass transistors are PMOS transistors.

19. The CAM cell of claim 15 , wherein the compare circuit further comprises:

first and second gating transistors connected in parallel between the gate of the first match line pull-down transistor and ground potential, the first gating transistor having a gate to receive the mask bit, and the second gating transistor having a gate to receive the comparand bit.

20. The CAM cell of claim 19 , wherein the compare circuit farther comprises:

third and fourth gating transistors connected in parallel between the gate of the second match line pull-down transistor and ground potential, the third gating transistor having a gate to receive the mask bit, and the fourth gating transistor having a gate to receive the complemented comparand bit.

21. The CAM cell of claim 20 , wherein the gating transistors are NMOS transistors.