Busy detection logic for asynchronous communication port
View Patent ↗An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.
1. A circuit, comprising
first logic coupled to receive request signals generated in a first time domain, and configured to store selected of the request signals responsive to a strobe signal of the request signals;
synchronizing logic configured to synchronize the stored request signals to a second time domain to generate synchronized request signals; and
load logic coupled to output the synchronized request signals according to a predetermined priority.
2. The circuit of claim 1 , wherein: each of the selected of the request signals corresponds to different resource accessed in response to the load logic.
3. The circuit of claim 1 , wherein: the selected of the request signals are predetermined address values for at least one memory device.
4. The circuit of claim 3 , wherein: the other of the request signals includes a read/write signal for the at least one memory device.
5. The circuit of claim 1 , wherein: the selected of the request signals are port identification values of a multi-port memory system.
6. The circuit of claim 1 , wherein: the first logic comprises a plurality of trigger flip-flops (FFs), each trigger FF having an input coupled to receive one of the selected of the request signals, an output coupled to the synchronizing logic, and an enable input coupled to the other of the request signals.
7. The circuit of claim 6 , wherein: the synchronizing logic comprises a plurality of flip-flop (FF) chains, each FF chain having multiple FF in series with one another operating in the second time domain, and a chain input coupled to an output of each trigger FF.
8. The circuit of claim 1 , further including: clear logic configured to remove one of the synchronized request signal after the synchronized request signal has been output by the load logic.
9. A method, comprising:
receiving a plurality of input signals;
capturing a state of selected input signals responsive to a timing signal of the plurality of input signals;
synchronously clocking the captured states along separate logic paths; and
outputting the captured states according to a predetermined priority.
10. The method of claim 9 , wherein: receiving the plurality of input signals includes receiving memory access requests.
11. The method of claim 10 , wherein: capturing the state of selected input signals includes any selected from: capturing address values and capturing input signals generated in response to address values.
12. The method of claim 10 , wherein capturing a state of selected input signals responsive to the timing signal of the input signals includes capturing selected input signals in response to a rising or falling edge of a read or write request signal.
13. The method of claim 10 , wherein: the captured states include both an active state and an inactive state; and outputting the captured states according to a predetermined priority includes providing only one active captured state at one time.
14. The method of claim 9 , further including: each captured state corresponds to a different resource; and clearing the captured state in response to an indication that the corresponding resource has been accessed.
15. The method of claim 9 , further including: each captured state corresponds to a different resource; and clearing the captured state in response to an indication that the corresponding resource has been accessed.
16. A system, comprising:
a first device;
a second device having a plurality of different resources accessible by the first device, and operating in a first clock domain; and
a logic unit coupled between the first and second devices configured to latch resource request signals from the first device in response to a timing signal of the resource request signals, and synchronize latched resource request signals to the first clock domain.
17. The system of claim 16 , wherein: the first device comprises a processor.
18. The system of claim 16 , wherein: the second device comprises a memory device; the resource request input signals identify different ports of the memory device; and the timing signal is a read or write request signal.
19. The system of claim 18 , further including: at least one buffer configured to transfer data corresponding to different port between the first and second devices in response to at least the latched request signals.
20. The system of claim 16 , wherein: the logic unit further includes clear logic configured to remove the latched resource request signal for a resource after the first device has accessed the resource in response to such a resource request signal.