Method for fabricating semiconductor device

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming a dummy gate on the substrate;

forming a contact etch stop layer on the dummy gate and the substrate, wherein the contact etch stop layer comprises a tensile stress layer;

forming an interlayer dielectric layer on the tensile stress layer;

performing a planarizing process to partially remove the interlayer dielectric layer and the contact etch stop layer;

partially removing the dummy gate; and

after removing the dummy gate, performing a thermal treatment on both the contact etch stop layer and the interlayer dielectric layer.

2. The method of claim 1 , wherein the planarizing process comprises a chemical mechanical polishing process.

3. The method of claim 1 , wherein the thermal treatment comprises a spike anneal process.

4. The method of claim 1 , wherein the thermal treatment comprises a millisecond anneal process.

5. The method of claim 1 , wherein the thermal treatment comprises a UV curing process.

6. The method of claim 1 , wherein the contact etch stop layer is a tensile stress contact etch stop layer.

7. The method of claim 1 , wherein the semiconductor device comprises an NMOS transistor.

8. The method of claim 1 , wherein the contact etch stop layer comprises a thickness between 50 Angstroms to 200 Angstroms.

9. The method of claim 1 , wherein the dummy gate comprises an interfacial layer, a high-k dielectric layer, and a polysilicon layer.

10. The method of claim 9 , further comprising:

forming a source/drain region in the substrate adjacent to two sides of the dummy gate before forming the contact etch stop layer;

forming a silicide layer on the source/drain region;

covering an interlayer dielectric layer on the contact etch stop layer;

removing the polysilicon layer of the dummy gate to form a recess in the interlayer dielectric layer;

performing the thermal treatment on the contact etch stop layer; and

depositing a work function layer, a barrier layer, and a conductive layer in the recess for forming a gate.

11. The method of claim 10 , wherein after forming the gate further comprises:

forming a plurality of contact vias in the dielectric layer; and

forming a silicide layer in the contact vias.

12. The method of claim 1 , further comprising forming a spacer on the sidewall of the dummy gate.

13. The method of claim 12 , further comprising forming the contact etch stop layer on the dummy gate, the substrate, and the spacer.

14. The method of claim 1 , further comprising:

forming a source/drain region in the substrate adjacent to two sides of the dummy gate before forming the contact etch stop layer;

forming a silicide layer on the source/drain region;

covering an interlayer dielectric layer on the contact etch stop layer;

partially removing the dummy gate to form a recess in the interlayer dielectric layer;

performing the thermal treatment on the contact etch stop layer; and

forming a gate in the recess, wherein the gate comprises a high-k dielectric layer, a work function layer, a barrier layer, and a conductive layer.

15. The method of claim 14 , wherein the high-k dielectric layer comprises a U-shaped high-k dielectric layer.

16. The method of claim 14 , wherein after forming the gate further comprises:

forming a plurality of contact vias in the dielectric layer; and

forming a silicide layer in the contact vias.