TAM with scan frame copy register coupled with serial output
Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.
1. An integrated circuit comprising;
A. core circuitry having scan paths, the scan paths including scan data input leads, scan data output leads, and scan control input leads; and
B. a test access mechanism having:
i. a serial data input lead;
ii. a serial data output lead;
iii. parallel data output leads coupled to the to the scan data input leads;
iv. parallel data input leads coupled to the scan data output leads;
v. control output leads coupled to the scan control input leads;
vi. a clock signal input;
vii. a functional clock signal input;
viii. a test/read input;
ix. a test access mechanism enable input; and
x. a scan frame copy register having an output coupled with the serial data output lead, the scan frame copy register including a stimulus section, a mask section, a command section, and a frame marker section.
2. The integrated circuit of claim 1 including a controller coupled with the clock signal input, the test/read input, the test access mechanism enable input, and the control output leads.
3. The integrated circuit of claim 1 in which the test access mechanism includes a scan frame input register having an input coupled with the serial data input lead.
4. The integrated circuit of claim 1 in which the test access mechanism includes a scan frame update register having outputs coupled with the parallel data output leads.
5. The integrated circuit of claim 1 in which the test access mechanism includes compressor circuitry having a serial input coupled with the serial data input lead, a serial output coupled with the serial data output lead, and parallel inputs coupled with the parallel data input leads.