Semiconductor device having metal gate and manufacturing method thereof
View Patent ↗A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
1. A semiconductor device having a metal gate comprising:
a substrate having a first gate trench and a second gate trench formed thereon;
a gate dielectric layer respectively formed in the first gate trench and the second gate trench;
a first work function metal layer formed in the first gate trench;
an inter layer formed between the gate dielectric layer and the first work function metal layer, the inter layer directly contacting the first work function metal layer and the gate dielectric layer, respectively;
a second work function metal layer respectively formed in the first gate trench and the second gate trench, an upper area of the second work function metal layer in the first gate trench being larger than an upper area of the first work function metal layer in the first gate trench;
a filling metal layer formed on the first work function metal layer and the second work function metal layer;
wherein the inter layer has a height extending only to a height of the first work function metal in the first gate trench and with an upper edge directly contacting the upper area of the second work function metal in the first gate trench.
2. The semiconductor device according to claim 1 , wherein the gate dielectric layer comprises a high-K gate dielectric layer.
3. The semiconductor device according to claim 2 , wherein the high-K gate dielectric layer and the inter layer comprise an “U” shape or a “—” shape.
4. The semiconductor device according to claim 1 , wherein the inter layer comprises a barrier layer, strained stress layer, a tuning metal layer, or the combination thereof.
5. The semiconductor device according to claim 1 , wherein the first work function metal layer comprises an “U” shape.
6. The semiconductor device according to claim 1 , wherein the second work function metal layer in the first gate trench is formed between the first work function metal layer and the filling metal layer.
7. The semiconductor device according to claim 1 , wherein an opening width of the second gate trench is larger than an opening width of the first gate trench.
8. The semiconductor device according to claim 7 , further comprising a third gate opening formed on the substrate, wherein the opening width of the second gate opening is larger than an opening width of the third gate opening, and the gate dielectric layer, the second work function metal layer, and the filling metal layer are formed in the third gate opening.