Profiling-based scan chain diagnosis

1. A method of scan chain diagnosis, executed by at least one processor of a computer, comprising:

by a tester that is separate from a circuit under test:

applying scan patterns to the circuit under test;

based on unloading masking information, collecting test response data from the circuit under test for sensitive unloading bits and not collecting test response data from the circuit under test for at least some non-sensitive unloading bits;

performing a profiling-based analysis to determine failing scan cell information based on the test response data for sensitive unloading bits; and

storing the failing scan cell information in a tangible processor-accessible medium, or displaying the failing scan cell information on a tangible medium.

2. The method recited in claim 1 , wherein the unloading masking information for each of the scan patterns is determined by a method of unloading masking information generation, the method of unloading masking information generation comprising:

masking sensitive loading bits to generate a masked scan pattern for each of the scan chains for each of a plurality of fault models for each of the scan patterns;

simulating the masked scan pattern for each of scan chains for each of the plurality of fault models for each of the scan patterns;

identifying the sensitive unloading bits for each of the plurality of fault models for each of the scan patterns based on results of the simulating;

determining general sensitive unloading bits for each of the scan patterns by combining the sensitive unloading bits for each of the plurality of fault models for each of the scan patterns; and

storing information of the general sensitive unloading bits for each of the scan patterns as the unloading masking information for each of the scan patterns in a tangible processor-accessible medium.

3. The method recited in claim 1 , wherein the unloading masking information for each of the scan patterns is determined by a method of unloading masking information generation, the method of unloading masking information generation comprising:

masking sensitive loading bits to generate a masked scan pattern for each of the scan chains for each of a plurality of fault models for each of the scan patterns;

simulating the masked scan pattern for each of scan chains for each of the plurality of fault models for each of the scan patterns; and

identifying the sensitive unloading bits for each of the scan chains for each of the plurality of fault models for each of the scan patterns based on results of the simulating.

4. The method recited in claim 3 , wherein the method of unloading masking information generation further comprises:

determining, based on faulty scan chain information, adaptive sensitive unloading bits for each of the scan patterns from the sensitive unloading bits for each of the scan chains for each of the plurality of fault models for each of the scan patterns; and

storing information of the adaptive sensitive unloading bits for each of the scan patterns as the unloading masking information for each of the scan patterns in a tangible processor-accessible medium.

5. The method recited in claim 3 , wherein the method of unloading masking information generation further comprises:

determining general sensitive unloading bits for each of the scan chains for each of the scan patterns by combining the sensitive unloading bits for each of the scan chain for each of the plurality of fault models for each of the scan patterns;

determining, based on faulty scan chain information, adaptive general sensitive unloading bits for each of the scan patterns from the general sensitive unloading bits for each of the scan chains for each of the scan patterns; and

storing information of the adaptive general sensitive unloading bits for each of the scan patterns as the unloading masking information for each of the scan patterns in a tangible processor-accessible medium.

6. The method recited in claim 5 , wherein the faulty scan chain information is generated by applying chain patterns to the circuit under test.

7. The method recited in claim 1 , wherein the performing profiling-based analysis comprises:

determining scan cell failing probability information for one or more faulty scan chains of the circuit under test based on the test response data for each of the scan patterns and expected test response data for each of the scan patterns; and

determining failing scan cell information based on the scan cell failing probability information.

8. The method recited in claim 7 , wherein the one or more faulty scan chains are determined by applying chain patterns to the circuit under test.

9. The method recited in claim 7 , wherein the expected test response data are derived by a masking simulation method, the masking simulation method comprises:

masking sensitive loading bits for each of the scan patterns; and

simulating each of masked scan patterns.

10. One or more computer-readable storage devices storing computer-executable instructions which when executed by a computer cause the computer to perform a method of scan chain diagnosis, the method comprising:

by a tester that is separate from a circuit under test:

applying scan patterns to the circuit under test;

based on unloading masking information, collecting test response data from the circuit under test for sensitive unloading bits and not collecting test response data from the circuit under test for at least some non-sensitive unloading bits; and

performing a profiling-based analysis to determine failing scan cell information based on the test response data for sensitive unloading bits.

11. The one or more computer-readable storage devices of claim 10 , wherein the unloading masking information for each of the scan patterns is determined by a method of unloading masking information generation, the method of unloading masking information generation comprising:

masking sensitive loading bits to generate a masked scan pattern for each of the scan chains for each of a plurality of fault models for each of the scan patterns;

simulating the masked scan pattern for each of scan chains for each of the plurality of fault models for each of the scan patterns;

identifying the sensitive unloading bits for each of the plurality of fault models for each of the scan patterns based on results of the simulating; and

determining general sensitive unloading bits for each of the scan patterns by combining the sensitive unloading bits for each of the plurality of fault models for each of the scan patterns.

12. The one or more computer-readable storage devices of claim 10 , wherein the unloading masking information for each of the scan patterns is determined by a method of unloading masking information generation, the method of unloading masking information generation comprising:

masking sensitive loading bits to generate a masked scan pattern for each of the scan chains for each of a plurality of fault models for each of the scan patterns;

simulating the masked scan pattern for each of scan chains for each of the plurality of fault models for each of the scan patterns; and

identifying the sensitive unloading bits for each of the scan chains for each of the plurality of fault models for each of the scan patterns based on results of the simulating.

13. The one or more computer-readable storage devices of claim 12 , wherein the method of unloading masking information generation further comprises:

determining, based on faulty scan chain information, adaptive sensitive unloading bits for each of the scan patterns from the sensitive unloading bits for each of the scan chains for each of the plurality of fault models for each of the scan patterns; and

storing information of the adaptive sensitive unloading bits for each of the scan patterns as the unloading masking information for each of the scan patterns in a tangible processor-accessible medium.

14. The one or more computer-readable storage devices of claim 12 , wherein the method of unloading masking information generation further comprises:

determining general sensitive unloading bits for each of the scan chains for each of the scan patterns by combining the sensitive unloading bits for each of the scan chain for each of the plurality of fault models for each of the scan patterns;

determining, based on faulty scan chain information, adaptive general sensitive unloading bits for each of the scan patterns from the general sensitive unloading bits for each of the scan chains for each of the scan patterns; and

storing information of the adaptive general sensitive unloading bits for each of the scan patterns as the unloading masking information for each of the scan patterns in a tangible processor-accessible medium.

15. The one or more computer-readable storage devices of claim 14 , wherein the faulty scan chain information is generated by applying chain patterns to the circuit under test.

16. The one or more computer-readable storage devices of claim 10 , wherein the performing profiling-based analysis comprises:

determining scan cell failing probability information for one or more faulty scan chains of the circuit under test based on the test response data for each of the scan patterns and expected test response data for each of the scan patterns; and

determining failing scan cell information based on the scan cell failing probability information.

17. The one or more computer-readable storage devices of claim 16 , wherein the one or more faulty scan chains are determined by applying chain patterns to the circuit under test.

18. The one or more computer-readable storage devices of claim 17 , wherein the expected test response data are derived by a masking simulation method, the masking simulation method comprises:

masking sensitive loading bits for each of the scan patterns; and

simulating each of masked scan patterns.