Memory cells with rectifying device
View Patent ↗Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.
1. A method, comprising:
activating an access line to select a plurality of access nodes in a memory array;
selecting a memory cell in a memory block, wherein there are multiple resistance changing cells, each phase change cell formed from edge portions of a continuous structure associated with each access node; and
detecting an electrical signal that passes through a rectifying device and a respective one of the memory cells.
2. The method of claim 1 , wherein an access transistor is associated with each access node.
3. The method of claim 1 , wherein the multiple resistance chan in cells include chalcogenide glass.
4. The method of claim 1 , wherein the memory block includes two memory cells.
5. The method of claim 1 , wherein the memory block includes four memory cells.
6. A method, comprising:
activating a plurality of access transistors in a memory array;
selecting a memory cell in a memory block, wherein there are multiple phase change cells, each phase change cell formed from edge portions of a continuous structure associated with each access transistor; and
detecting an electrical signal that passes through a rectifying device and a respective one of the memory cells.
7. The method of claim 6 , wherein the memory block includes four memory cells.
8. The method of claim 7 , wherein selecting comprises selecting according to a selection rule.
9. The method of claim 8 , wherein selecting according to the selection rule comprises L=2*m+4*n+k;
wherein m is a row number in the memory array and n is a column number in the memory array, and m and n determine the desired access transistor;
wherein k is an individual cell in the four cell memory block and k is chosen from a group consisting of 1, 2, 3, and 4; and
wherein L is an electrode select line number.
10. The method of claim 8 , wherein selecting according to the selection rule comprises L=2*m+2*n+k;
wherein m is a row number in the memory array and n is a column number in the memory array, and m and n determine the desired access transistor;
wherein k is an individual cell in the four cell memory block and k is chosen from a group consisting of 1, 2, 3, and 4; and
wherein L is an electrode select line number.
11. The method of claim 8 , wherein selecting according to the selection rule comprises L=m+2*n+k−3;
wherein m is a row number in the memory array and n is a column number in the memory array, and m and n determine the desired access transistor;
wherein k is an individual cell in the four cell memory block and k is chosen from a group consisting of 1, 2, 3, and 4; and
wherein L is an electrode select line number.
12. A method, comprising:
activating an access line to select a plurality of access nodes in a memory array;
selecting a memory cell in a memory block, wherein there are multiple resistance changing cells formed from portions of a continuous ring-like structure associated with each access node; and
detecting an electrical signal that passes through a rectifying device and a respective one of the memory cells.
13. The method of claim 12 , wherein the memory cells include phase changing cells.
14. The method of claim 12 , wherein selecting comprises selecting according to a selection rule.
15. The method of claim 14 , wherein selecting according to the selection rule comprises L=2*m+4*n+k;
wherein m is a row number in the memory array and n is a column number in the memory array, and m and n determine the desired access transistor;
wherein k is an individual cell in the four cell memory block and k is chosen from a group consisting of 1, 2, 3, and 4; and
wherein L is an electrode select line number.
16. The method of claim 14 , wherein selecting according to the selection rule comprises L=2*m+2*n+k;
wherein m is a row number in the memory array and n is a column number in the memory array, and m and n determine the desired access transistor;
wherein k is an individual cell in the four cell memory block and k is chosen from a group consisting of 1, 2, 3, and 4; and
wherein L is an electrode select line number.
17. The method of claim 14 , wherein selecting according to the selection rule comprises L=m+2*n+k−3;
wherein m is a row number in the memory array and n is a column number in the memory array, and m and n determine the desired access transistor;
wherein k is an individual cell in the four cell memory block and k is chosen from a group consisting of 1, 2, 3, and 4; and
wherein L is an electrode select line number.
18. The method of claim 12 , wherein detecting the electrical signal that passes through the rectifying device includes detecting an electrical signal that passes through a diode.
19. The method of claim 12 , wherein an access transistor is associated with each access node.