Level shifter

1. A level shifter comprising:

a driving signal generating unit configured to generate a pull-up signal and a pull-down signal in response to an input signal, wherein the input signal swings between a first high level and a first low level;

a driving unit configured to generate an output signal swinging between a second high level and a second low level in response to the pull-up signal and the pull-down signal; and

a current path forming unit configured to form a current path between the pull-up signal and the pull-down signal in response to the pull-up signal and the pull-down signal,

wherein the current path forming unit comprises a first diode configured transistor to be turned on to transfer the level of the pull-up signal to the pull-down signal when the pull-up signal is driven to the first low level, and a second diode configured transistor to be turned on to transfer the level of the pull-down signal to the pull-up signal when the pull-down signal is driven to the first high level.

2. The level shifter of claim 1 , wherein when the input signal is at the first high level, the driving signal generating unit drives the pull-up signal to the first low level.

3. The level shifter of claim 2 , wherein when the input signal is at the first low level, the driving signal generating unit drives the pull-down signal to the first high level.

4. The level shifter of claim 1 , wherein the driving signal generating unit drives the pull-up signal and the pull-down signal in response to the output signal.

5. The level shifter of claim 1 , wherein when the output signal is at the second high level, the driving signal generating unit drives the pull-down signal to the second low level.

6. The level shifter of claim 1 , wherein when the output signal is at the second low level, the driving signal generating unit drives the pull-up signal to the second high level.

7. The level shifter of claim 1 , wherein the driving signal generating unit comprises:

a first driving element configured to drive the pull-up signal to the second high level when the output signal is at the second low level;

a second driving element configured to drive the pull-up signal to the first low level when the input signal is at the first high level;

a third driving element configured to drive the pull-down signal to the first high level when the input signal is at the first low level; and

a fourth driving element configured to drive the pull-down signal to the second low level when the output signal is at the second high level.

8. The level shifter of claim 1 , wherein the second high level is higher than the first high level, and the second low level is lower than the first low level.

9. The level shifter of claim 1 , wherein when the pull-up signal is driven to the first low level, the driving unit is turned on to drive the output signal to the second high level.

10. The level shifter of claim 1 , wherein when the pull-down signal is driven to the first high level, the driving unit is turned on to drive the output signal to the second low level.

11. The level shifter of claim 1 , wherein the driving unit comprises:

a pull-up driving element configured to be turned on to pull-up drive the output signal to the second high level when the pull-up signal is driven to the first low level; and

a pull-down driving element configured to be turned on to pull-down drive the output signal to the second low level when the pull-down signal is driven to the first high level.

12. The level shifter of claim 1 , wherein when the pull-up signal is driven to the first low level, the current path forming unit is turned on to transfer the level of the pull-up signal to the pull-down signal.

13. The level shifter of claim 1 , wherein when the pull-down signal is driven to the first high level, the current path forming unit is turned on to transfer the level of the pull-down signal to the pull-up signal.

14. The level shifter of claim 1 , wherein when the input signal is at the first high level, the driving signal generating unit drives the pull-up signal to the first low level, the current path forming unit transfers the level of the pull-up signal to the pull-down signal, and the driving unit drives the output signal to the second high level.

15. The level shifter of claim 1 , wherein when the input signal is at the first low level, the driving signal generating unit drives the pull-down signal to the first high level, the current path forming unit transfers the level of the pull-down signal to the pull-up signal, and the driving unit drives the output signal to the second low level.

16. A level shifting transistor circuit comprising:

a substrate and a source terminal of a first PMOS transistor are coupled to a second high voltage rail;

a drain terminal of the first PMOS transistor is coupled to a drain terminal of a first NMOS transistor, a gate terminal of a third PMOS transistor, a drain terminal of a fourth NMOS transistor, and a gate terminal and a source terminal of a fourth PMOS transistor;

a substrate and a source terminal of the first NMOS transistor are coupled to a first low voltage rail;

a gate terminal of each of the first NMOS transistor and a second PMOS transistor is coupled to an input node;

a substrate and a source terminal of the second PMOS transistor are coupled to a first high voltage rail;

a drain terminal of the second PMOS transistor is coupled to a drain terminal of a second NMOS transistor, a gate terminal and a source terminal of the fourth NMOS transistor, a drain terminal of the fourth PMOS transistor, and a gate terminal of a third NMOS transistor;

a substrate and a source terminal of the second NMOS transistor are coupled to the second low voltage rail;

a substrate and a source terminal of the third PMOS transistor are coupled to the second high voltage rail;

a drain terminal of the third PMOS transistor is coupled to a gate terminal of the first PMOS transistor, a gate terminal of the second NMOS transistor, a drain terminal of the third NMOS transistor, and an output node;

a substrate and a source terminal of the third NMOS transistor are coupled to the second low voltage rail;

a substrate of the fourth NMOS transistor is coupled to the first low voltage rail; and

a substrate of the fourth PMOS transistor is coupled to the first high voltage rail.