Semiconductor structure having metal-insulator-metal capacitor structure
A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A first etch stop layer is disposed over the TSV structure. A first dielectric layer is disposed in contact with the first etch stop layer. A first conductive structure is disposed through the first etch stop layer and the first dielectric layer. The first conductive structure is electrically coupled with the TSV structure. The TSV structure is substantially wider than the first conductive structure. A second etch stop layer is disposed in contact with the first dielectric layer. A metal-insulator-metal (MIM) capacitor structure is disposed in contact with the second etch stop layer.
1. A semiconductor structure comprising:
a through-substrate-via (TSV) structure disposed in a substrate;
a first etch stop layer disposed over the TSV structure;
a first dielectric layer disposed in contact with the first etch stop layer;
a first conductive structure disposed through the first etch stop layer and the first dielectric layer, the first conductive structure being electrically coupled with the TSV structure, wherein the TSV structure is substantially wider than the first conductive structure;
a second etch stop layer disposed in contact with the first dielectric layer; and
a metal-insulator-metal (MIM) capacitor structure disposed in contact with the second etch stop layer.
2. The semiconductor structure of claim 1 , further comprising:
a second dielectric layer disposed over the MIM capacitor structure; and
a second conductive structure disposed in the second dielectric layer, the second conductive structure being electrically coupled with the first conductive structure, wherein the second conductive structure is substantially wider than the first conductive structure.
3. The semiconductor structure of claim 2 , wherein the first conductive structure and the second conductive structure constitute a dual damascene structure, the first conductive structure is a via portion of the dual damascene structure, and the second conductive structure is a trench portion of the dual damascene structure.
4. The semiconductor structure of claim 2 , wherein the first dielectric layer is a via inter metal dielectric (IMD) layer and the second dielectric layer is a trench IMD layer.
5. The semiconductor structure of claim 1 , further comprising:
a third conductive structure disposed between the TSV structure and the first etch stop layer, the third conductive structure being electrically coupled with the first conductive structure, wherein the third conductive structure is substantially wider than the first conductive structure.
6. The semiconductor structure of claim 5 , wherein the third conductive structure is wider than the TSV structure.
7. The semiconductor structure of claim 5 , further comprising:
a cap layer disposed over the MIM capacitor structure, wherein the third conductive structure is disposed through the second dielectric layer, the second etch stop layer and the cap layer.
8. The semiconductor structure of claim 1 , wherein the first conductive structure is not configured to provide electrical routing in the first dielectric layer.