Semiconductor device including cell region and peripheral region having high breakdown voltage structure
A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.
1. A semiconductor device comprising:
a semiconductor substrate including a substrate, a drift layer of a first conductivity type disposed on a surface of the substrate, and a base layer of a second conductivity type disposed on a surface of the drift layer; and
an electric field terminal part, wherein
the semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region,
the base region has a bottom face located on a same plane throughout the cell region and the peripheral region,
a portion of the base region located in the peripheral region provides an electric field relaxing layer,
the electric field terminal part is disposed in the peripheral region, the electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer, and
the electric field terminal part penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer, wherein the electric field relaxing layer reaches a channel forming part of the cell region.
2. The semiconductor device according to claim 1 , wherein
the electric field terminal part includes at least one groove penetrating the electric field relaxing layer from the surface of the electric field relaxing layer to the drift layer and an insulating member disposed in the at least one groove.
3. The semiconductor device according to claim 2 , wherein
the at least one groove includes a plurality of grooves,
the insulating member is disposed in each of the plurality of grooves, and
the plurality of grooves concentrically surrounds the cell region and the portion of the electric field relaxing layer.
4. The semiconductor device according to claim 1 , wherein
the electric field terminal part includes a first conductivity type layer that penetrates the electric field relaxing layer from the surface of the electric field relaxing layer to the drift layer.
5. The semiconductor device according to claim 1 , wherein
the semiconductor substrate has a recess section in the peripheral region,
the recess section is formed by removing a portion of the base layer from a surface of the base layer so as to form a mesa structure, and
the electric field terminal part is disposed in the recess section.
6. The semiconductor device according to claim 1 , wherein
the semiconductor substrate has a recess section in the peripheral region,
the recess section is formed by removing a portion of the base layer from a surface of the base layer so as to form a mesa structure, and
the electric field terminal part is disposed outside the recess section.
7. The semiconductor device according to claim 5 , wherein
the recess section has a stepped portion adjacent to the cell region, and
the electric field terminal part is located at a distance of from 1 μm to 1000 μm from the stepped portion.
8. The semiconductor device according to claim 1 , wherein
the base layer and the electric field relaxing layer have an impurity concentration of from 1×10 16 cm −3 to 2.5×10 17 cm −3 .
9. The semiconductor device according to claim 1 , wherein:
the semiconductor element in the cell region is a NPN transistor.
10. The semiconductor device according to claim 9 , wherein:
the NPN transistor includes a gate electrode in a trench via an insulating layer, a source region attached to the trench and disposed in a surface portion of the base layer, and a drain electrode disposed on a substrate,
the trench penetrates the base layer and reaches the drift layer,
the channel forming part of the cell region is disposed between the source region and the drift layer in the base layer, and attached to a sidewall of the trench.
11. The semiconductor device according to claim 1 , wherein:
the base layer includes a plurality of thicknesses.
12. The semiconductor device according to claim 11 , wherein:
the plurality of thicknesses includes a first thickness of a first part of the base layer and a second thickness of a second part of the base layer;
the first part is nearer the cell region than the second part; and
the first thickness is larger than the second thickness.
13. The semiconductor device according to claim 1 , wherein:
the electric field relaxing layer reaches the channel forming part of the cell region through the portion of the base layer located in the peripheral region that provides the electric field relaxing layer.
14. The semiconductor device according to claim 1 , wherein:
the electric field relaxing layer does not have a bending portion.
15. The semiconductor device according to claim 1 , wherein:
of all device semiconductor layers, only the drift layer is in contact with the electric field relaxing layer.