Programmable micro-core processors for packet parsing with packet ordering
View Patent ↗Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers. A dependency list is used to maintain proper ordering of packets being processed by the micro-cores.
1. A system for processing packets, comprising:
a plurality of micro-cores configured to process the packets; and
a memory to store a dependency list comprising a structure configured to maintain an order in which the packets are to be processed and released,
wherein the dependency list comprises a plurality of rows and a plurality of columns,
wherein each micro-core of the plurality of micro-cores is associated with a corresponding row from among the plurality of rows and a corresponding column from among the plurality of columns,
wherein the corresponding row is configured to hold data identifying whether a given packet associated with the corresponding row has dependencies on one or more other packets, and
wherein the corresponding column is configured to hold data identifying whether a given packet associated with the corresponding column creates dependencies for one or more other packets.
2. The system of claim 1 , wherein the structure is further configured to hold a bit vector associated with a packet, from among the packets, that is being processed by a micro-core from among the plurality of micro-cores,
wherein bits in the bit vector identify an existence of a dependency.
3. The system of claim 1 , wherein the memory comprises content addressable memory.
4. A method to maintain ordering when processing packets, comprising:
using a plurality of micro-cores to process the packets; and
maintaining an order in which the packets are to be processed and released using a dependency list stored in a memory, the dependency list comprising a structure having a set of rows and a set of columns to maintain the order in which the packets are to be processed and released,
wherein each micro-core from the plurality of micro-cores is associated with both a corresponding row from the set of rows and a corresponding column from the set of columns,
wherein the corresponding row holds data identifying whether a given packet associated with the corresponding row has dependencies on one or more other packets, and
wherein the corresponding column holds data identifying whether a given packet associated with the corresponding column creates dependencies for one or more other packets.
5. The method of claim 4 , wherein the corresponding row holds a bit vector associated with a packet, from among the packets, that is being processed by a micro-core from among the plurality of micro-cores,
wherein bits in the bit vector identify an existence of a dependency.
6. The method of claim 5 , wherein each bit of the bit vector corresponds to the dependency for a different packet.
7. The method of claim 4 , further comprising:
receiving a packet from among the packets for processing by a micro-core from among the plurality of micro-cores;
associating the corresponding row with the micro-core; and
adding a value in the corresponding row to indicate whether the packet has a dependency on another packet.
8. The method of claim 7 , wherein the value comprises a bit vector with bit values that correspond to rows from among the set of rows associated with other micro-cores from among the plurality of micro-cores.
9. The method of claim 4 , further comprising:
receiving a request to release a packet, from among the packets, that was processed by a micro-core from among the plurality of micro-cores;
checking a row from the set of rows associated with the micro-core to identify a dependency for the packet on another packet from among the packets; and
releasing the packet if the dependency is not identified.
10. The method of claim 9 , wherein a bit vector in the row is checked to identify a value indicating the dependency.
11. The method of claim 9 , wherein a second packet from among the packets is dependent on the packet, and a second row from among the set of rows is associated with the second packet,
wherein a value in the second row indicates a dependency of the second packet on the packet, and wherein release of the packet causes a value in the second row to be modified to indicate no further dependency on the packet.
12. The system of claim 1 , wherein, based on the dependency list, the plurality of micro-cores is configured to release a later packet from among the packets from a flow after an earlier packet, from among the packets, from the flow has been processed.