Graphene or carbon nanotube devices with localized bottom gates and gate dielectric

1. A transistor device, comprising:

a substrate;

an insulator on the substrate;

a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator;

a local gate dielectric on the bottom gate;

a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and

conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

2. The device of claim 1 , wherein the carbon-based nanostructure material comprises a graphene or carbon nanotube layer.

3. The device of claim 1 , wherein the insulator comprises silicon dioxide.

4. The device of claim 1 , wherein the local bottom gate comprises a conductive material selected from the group consisting of doped polycrystalline silicon, doped single-crystal silicon, at least one metal and a layered stack of conductive materials.

5. The device of claim 1 , wherein the local gate dielectric comprises a material selected from the group consisting of an insulating oxide, an insulating nitride, an insulating oxynitride, and combinations comprising at least one of the foregoing materials in a layered configuration.

6. The device of claim 1 , further comprising:

a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.

7. The device of claim 4 , wherein the local bottom gate comprises palladium, and wherein the local gate dielectric comprises titanium oxide.

8. The device of claim 5 , wherein the local gate dielectric comprises silicon dioxide.

9. The device of claim 6 , wherein the local gate dielectric comprises silicon dioxide and the blanket gate dielectric comprises a metal oxide.

10. A method of fabricating a transistor device, comprising the steps of:

providing a substrate having an insulator thereon;

forming a local bottom gate in a trench in the insulator;

forming a local gate dielectric on the bottom gate;

forming a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and

forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

11. The method of claim 10 , further comprising the step of:

etching the trench in the insulator through a patterned resist layer.

12. The method of claim 10 , wherein the step of forming the local gate dielectric on the bottom gate comprises the step of:

oxidizing an upper portion of the bottom gate to form an oxide dielectric.

13. The method of claim 10 , further comprising the step of:

forming a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.

14. The method of claim 11 , wherein the step of forming the bottom-gate in the trench comprises the steps of:

blanket depositing a gate material onto the patterned resist layer and into the trench; and

removing the patterned resist layer and the gate material outside of the trench.

15. The method of claim 11 , further comprising the steps of:

blanket depositing a gate material onto the patterned resist layer and into the trench;

blanket depositing a gate dielectric material onto the gate material; and

removing the patterned resist layer along with portions of the gate material and portions of the gate dielectric material outside of the trench.

16. A method of fabricating a transistor device, comprising the steps of:

providing a wafer having a layer of electrically conductive material on an insulating layer;

forming cavities in the wafer to isolate one or more portions of the conductive material, wherein an isolated portion of the conductive material serves as a local bottom gate of the device;

filling the cavities with a dielectric;

forming a gate dielectric on the bottom gate;

forming a carbon-based nanostructure material over at least a portion of the gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and

forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

17. The method of claim 16 , wherein the layer of conductive material comprises a single crystal semiconductor-on-insulator layer and the insulating layer comprises a buried oxide.

18. The method of claim 16 , wherein the layer of conductive material comprises doped polycrystalline silicon.

19. The method of claim 16 , wherein the cavities extend into the insulating layer.

20. The method of claim 16 , wherein the cavities extend through the insulating layer.

21. The method of claim 16 , wherein the gate dielectric formed on the bottom gate is local to the bottom gate.

22. The method of claim 16 , wherein the step of forming the gate dielectric on the bottom gate comprises the step of:

blanket depositing a gate dielectric material on the bottom gate and on at least a portion of the dielectric filling the cavities.

23. The method of claim 16 , wherein the step of forming the gate dielectric on the bottom gate comprises the steps of:

forming a local gate dielectric on the bottom gate; and

forming a blanket gate dielectric on the local gate dielectric and at least a portion of the dielectric filling the cavities.

24. The method of claim 16 , wherein the step of forming the gate dielectric on the bottom gate comprises the step of:

oxidizing an upper portion of the bottom gate to form an oxide dielectric.