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App. No. 13/167,648 · Confirmation No. 8505

Method for Forming a Notched Gate Insulator for Advanced MIS Semiconductor Devices and Devices Thus Obtained

Abandoned -- Failure to Respond to an Office Action View Publication ↗
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2012-06-22 CTNF Non-Final Rejection 9 View
2012-06-22 892 List of references cited by examiner 1 View
2012-06-22 SRNT Examiner's search strategy and results 1 View
2012-06-22 FWCLM Index of Claims 1 View
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2011-12-22 NTC.PUB Notice of Publication 1 View
2011-09-15 WFEE Fee Worksheet (SB06) 1 View
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2011-09-15 PD.FILED.E Priority Documents electronically retrieved by USPTO from a participating IP Office 18 View
2011-09-06 PEFR Applicant Response to Pre-Exam Formalities Notice 3 View
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2011-09-06 WFEE Fee Worksheet (SB06) 2 View
2011-09-06 N417 Electronic Filing System Acknowledgment Receipt 2 View
2011-07-06 WFEE Fee Worksheet (SB06) 1 View
2011-07-06 APP.FILE.REC Filing Receipt 3 View
2011-07-06 NTC.MISS.PRT Notice to File Missing Parts 2 View
2011-06-23 ADS Application Data Sheet 5 View
2011-06-23 SPEC Specification 12 View
2011-06-23 CLM Claims 2 View
2011-06-23 ABST Abstract 1 View
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Quick Facts
App. No.
13/167,648
Filed
2011-06-23
Pub. No.
US20110309457A1
Examiner
LIN, JOHN
Art Unit
2815