Energy efficient ethernet (EEE) with 10GBASE-T structures
View Patent ↗An ethernet transceiver integrated circuit chip is disclosed including a plurality of transceivers for coupling to a corresponding plurality of physical channels. A channel switcher is coupled to the plurality of transceivers. During a first mode of operation, the channel switcher activates all of the plurality of transceivers to transceive data in accordance with a first aggregate data transfer rate. During a second mode of operation, the channel switcher activates less than all of the plurality of transceivers to transceive data in accordance with a second aggregate data rate that is less than the first aggregate data transfer rate.
1. An ethernet transceiver integrated circuit chip comprising:
a plurality of transceivers for coupling to a corresponding plurality of physical channels; and
a channel switcher coupled to the plurality of transceivers,
wherein during a first mode of operation, the channel switcher activates all of the plurality of transceivers to transceive data in accordance with a first aggregate data transfer rate within a range of 1 Gbps and 10 Gbps, and
wherein during a second mode of operation, the channel switcher activates less than all of the plurality of transceivers to transceive data in accordance with a second aggregate data rate within the range of 1 Gbps and 10 Gbps, that is less than the first aggregate data transfer rate.
2. The ethernet transceiver integrated circuit chip according to claim 1 wherein:
the plurality of transceivers comprises four transceivers.
3. The ethernet transceiver integrated circuit chip according to claim 1 wherein:
a symbol rate for data transferred by each transceiver during the first mode of operation is the same as the symbol rate for data transferred by each transceiver during the second mode of operation.
4. The ethernet transceiver integrated circuit chip according to claim 1 wherein:
a first symbol rate for data transferred by each transceiver during the first mode of operation is different than a second symbol rate for data transferred by each transceiver during the second mode of operation.
5. The ethernet transceiver integrated circuit chip according to claim 1 wherein the first mode of operation comprises a transmit mode, and the second mode of operation comprises a receive mode, and wherein:
during the transmit mode, all of the plurality of transceivers transceive data; and
during the receive mode, less than all of the transceivers transceive data.
6. An ethernet transceiver integrated circuit chip according to claim 1 comprising:
wherein the channel switcher activates a set of the plurality of transceivers to operate in a bidirectional mode, and
wherein the channel switcher activates at least one of the pluralit of transceivers not in the set to operate in a simplex mode.
7. The ethernet transceiver integrated circuit chip according to claim 6 wherein:
the plurality of transceivers transceive data in accordance with a first syMbol rate while operating in the bidirectional mode; and
the at least one of the plurality of transceivers operating in the simplex mode receives data in accordance with a second symbol rate.
8. The ethernet transceiver integrated circuit chip according to claim 7 wherein:
the first symbol rate is the same as the second symbol rate.
9. The ethernet transceiver integrated circuit chip according to claim 7 wherein:
the first symbol rate is different than the second symbol rate.
10. A method of operation in an ethernet integrated circuit chip, the method comprising:
in a first mode, transceiving data along a group of at least four twisted pair signaling channels in accordance with a first symbol rate for each channel and at a first data rate within a range of 1 Gbps and 10 Gbps; and
in a second mode, transceiving data at a second data rate within the range of 1 Gbps and 10 Gbps along a subset of the group of twisted pair signaling channels in accordance with the first symbol rate for each channel.