Tracking for read and inverse write back of a group of thyristor-based memory cells
View Patent ↗Method and integrated circuit for tracking for read and inverse write back of a group of thyristor-based memory cells is described. The method includes: reading the group of memory cells to obtain read data, and writing back opposite data states for the read data to the group of memory cells. The group of memory cells includes data cells and at least one check cell for check data, where the check data indicates polarity of the read data. The integrated circuit includes a grouping of memory cells of an array of memory cells including data cells and at least one check cell, and sense amplifiers. The at least one check cell is to track inversion/non-inversion status of the data cells associated therewith, and the sense amplifiers are coupled to obtain read information from the grouping and to write back data states opposite of those of the read information.
1. A method of operating a group of memory cells, comprising:
reading the group of memory cells to obtain read data;
the group of memory cells including data cells and at least one check cell;
the read data including check data associated with the at least one check cell;
writing back opposite data states for the read data to the group of memory cells; and
wherein the check data indicates polarity of the read data.
2. The method according to claim 1 , further comprising:
inverting the read data responsive to the check data to provide data read; and
outputting the data read.
3. The method according to claim 1 , further comprising:
at least three check cells, including the at least one check cell, for storing at least three check bits for the check data; and
initializing state of the check data all to a same data state.
4. The method according to claim 3 , wherein the group of memory cells is a group of thyristor-based memory cells.
5. The method according to claim 3 , wherein there is an odd integer number of the at least three check cells.
6. The method according to claim 3 , further comprising determining the polarity of the read data responsive to a majority state of the check data.
7. The method according to claim 1 , wherein:
the group of memory cells is a group of thyristor-based memory cells in an array coupled to a common wordline; and
the common wordline is coupled to either an anode or cathode emitter of each cell of multiple columns in the array.
8. The method according to claim 7 , wherein the group of thyristor-based memory cells are n-TCCT cells.
9. The method according to claim 7 , wherein the group of thyristor-based memory cells are p-TCCT cells.
10. The method according to claim 7 , wherein the common wordline is directly coupled to ground.
11. The method according to claim 7 , wherein the common wordline is directly coupled to an input/output supply voltage.
12. An integrated circuit, comprising:
an array of memory cells;
a grouping of memory cells of the array of memory cells including data cells and at least one check cell; and
the at least one check cell to track inversion/non-inversion status of the data cells associated therewith; and
sense amplifiers coupled to obtain read information from the grouping and to write back data states opposite of those of the read information.
13. The integrated circuit according to claim 12 , further comprising majority logic coupled to receive the read information from the at least one check cell and configured to provide a status signal of a majority data state of the read information of the at least one check cell.
14. The integrated circuit according to claim 13 , further comprising:
a data register coupled to the sense amplifiers;
select logic coupled to or part of the data register;
wherein the select logic is coupled to receive data out from the data registers and the indication from the majority logic; and
wherein the select logic is configured to output the data out in an inverted form or a non-inverted form responsive to the status signal.
15. The integrated circuit according to claim 12 , wherein the grouping of memory cells is a grouping of thyristor-based memory.
16. The integrated circuit according to claim 15 , wherein:
the grouping of thyristor-based memory cells are coupled to a common wordline to either anode or cathode emitters of each cell of thyristor-based memory cells; and
the common wordline is common to multiple columns of cells in the array of thyristor-based memory cells.
17. The integrated circuit according to claim 16 , wherein the array of thyristor-based memory cells are n-TCCT cells.
18. The integrated circuit according to claim 16 , wherein the thyristor-based memory cells are p-TCCT cells.
19. The integrated circuit according to claim 16 , wherein the common wordline is directly coupled to ground.
20. The integrated circuit according to claim 16 , wherein the common wordline is directly coupled to an input/output supply voltage.