Efficient wrapper cell design for scan testing of integrated
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip.
1. An integrated circuit comprising:
scan test circuitry; and
additional circuitry subject to testing utilizing the scan test circuitry;
the additional circuitry comprising at least first and second circuitry cores;
the scan test circuitry comprising a plurality of scan chains, including at least one wrapper cell scan chain arranged between the first and second circuitry cores, the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation;
wherein at least one of the wrapper cells of the wrapper cell scan chain comprises:
a flip-flop having a data input and a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores; and
a multiplexer having a functional path input, a scan shift input and an output; and
wherein the output of the multiplexer is coupled to the data input of the flip-flop and to a functional path input of the second circuitry core.
2. The integrated circuit of claim 1 wherein the first and second circuitry cores comprise respective read channel and additional cores of a system-on-chip.
3. The integrated circuit of claim 1 wherein the scan test circuitry is configured for separate scan testing of the first and second circuitry cores.
4. The integrated circuit of claim 3 wherein the wrapper cell scan chain is configured such that functional paths between the first circuitry core and the wrapper cell scan chain are scan tested in conjunction with scan testing of the first circuitry core and functional paths between the wrapper cell scan chain and the second circuitry core are scan tested in conjunction with scan testing of the second circuitry core.
5. The integrated circuit of claim 1 wherein:
the multiplexer has a select line;
the flip-flop has a data output;
the functional path input of the multiplexer is coupled to a functional path output of the first circuitry core;
the select line of the multiplexer is adapted to receive a scan shift enable signal;
the data output of the flip-flop is coupled to a scan shift input of another multiplexer in a next wrapper cell of the wrapper cell scan chain; and
the scan shift input of the multiplexer is coupled to a data output of another flip-flop of a previous wrapper cell of the wrapper cell scan chain.
6. The integrated circuit of claim 1 wherein the wrapper cell scan chain is configured such that a scan shift input of a given wrapper cell other than an initial wrapper cell of the wrapper cell scan chain is coupled to a data output of a flip-flop of a previous wrapper cell of the wrapper cell scan chain.
7. The integrated circuit of claim 1 wherein the wrapper cell scan chain is configured such that a data output of a flip-flop of a given wrapper cell other than a final wrapper cell of the wrapper cell scan chain is coupled to a scan shift input of a next wrapper cell of the wrapper cell scan chain.
8. The integrated circuit of claim 1 wherein the wrapper cell scan chain is configured such that at least one of the wrapper cells has a functional path input that is coupled to a functional path output of the first circuitry core and a functional path output that is coupled to the functional path input of the second circuitry core.
9. A hard disk drive controller comprising the integrated circuit of claim 1 .
10. A method of scan testing an integrated circuit, comprising:
controlling at least one wrapper cell scan chain arranged between first and second circuitry cores of the integrated circuit, the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation; and
scan testing functional paths between the first and second circuitry cores utilizing the wrapper cell scan chain;
wherein at least one of the wrapper cells of the wrapper cell scan chain comprises:
a flip-flop having a data input and a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores; and
a multiplexer having a functional path input, a scan shift input and an output; and
wherein the output of the multiplexer is coupled to the data input of the flip-flop and to a functional path input of the second circuitry core.
11. The method of claim 10 wherein said scan testing further comprises performing separate scan testing of the first and second circuitry cores.
12. The method of claim 11 wherein said scan testing further comprises scan testing functional paths between the first circuitry core and the wrapper cell scan chain in conjunction with scan testing of the first circuitry core and scan testing functional paths between the wrapper cell scan chain and the second circuitry core in conjunction with scan testing of the second circuitry core.
13. The method of claim 10 wherein the wrapper cell scan chain is configured such that a scan shift input of a given wrapper cell other than an initial wrapper cell of the wrapper cell scan chain is coupled to a data output of a flip-flop of a previous wrapper cell of the wrapper cell scan chain.
14. The method of claim 10 wherein the wrapper cell scan chain is configured such that a data output of a flip-flop of a given wrapper cell other than a final wrapper cell of the wrapper cell scan chain is coupled to a scan shift input of a next wrapper cell of the wrapper cell scan chain.
15. The method of claim 10 wherein the wrapper cell scan chain is configured such that at least one of the wrapper cells has a functional path input that is coupled to a functional path output of the first circuitry core and a functional path output that is coupled to the functional path input of the second circuitry core.
16. A computer program product comprising a non-transitory computer-readable storage medium having computer program code embodied therein for use in scan testing an integrated circuit, wherein the computer program code when executed in a testing system causes the testing system to perform the steps of the method of claim 10 .
17. A processing system comprising:
a processor; and
a memory coupled to the processor and configured to store information characterizing an integrated circuit design;
wherein the processing system is configured to modify the integrated circuit design by providing at least one wrapper cell scan chain arranged between first and second circuitry cores of the integrated circuit, the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation;
wherein at least one of the wrapper cells of the wrapper cell scan chain comprises:
a flip-flop having a data input and a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores; and
a multiplexer having a functional path input, a scan shift input and an output; and
wherein the output of the multiplexer is coupled to the data input of the flip-flop and to a functional path input of the second circuitry core.
18. An apparatus for use in scan testing an integrated circuit having first and second circuitry cores, the apparatus comprising:
a wrapper cell configurable with a plurality of other wrapper cells into a wrapper cell scan chain for arrangement between the first and second circuitry cores;
wherein the wrapper cell comprises:
a flip-flop having a data input and a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores; and
a multiplexer having a functional path input, a scan shift input and an output; and
wherein the output of the multiplexer is coupled to the data input of the flip-flop and to a functional path input of the second circuitry core.
19. The apparatus of claim 18 wherein:
the multiplexer has a select line;
the flip-flop has a output;
the functional path input of the multiplexer is coupled to a functional path output of the first circuitry core;
the select line of the multiplexer is adapted to receive a scan shift enable signal;
the data output of the flip-flop is coupled to a scan shift input of another multiplexer in a next wrapper cell of the wrapper cell scan chain; and
the scan shift input of the multiplexer is coupled to a data output of another flip-flop of a previous wrapper cell of the wrapper cell scan chain.
20. The apparatus of claim 18 wherein the flip-flop is a non-resettable flip-flop.