IP Library Granted Patent US 8,378,454
Granted Patent B2
US 8,378,454 · App. 13/173,709 · Granted Feb 19, 2013

Semiconductor device including metal-insulator-metal capacitor arrangement

Inventors: Masayuki Furumiya (Kanagawa, JP); Kuniko Kikuta (Kanagawa, JP); Ryota Yamamoto (Kanagawa, JP); Makoto Nakayama (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,378,454
App. No.
13/173,709
Granted
Feb 19, 2013
Kind
B2
Abstract

A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

Claims (16)

1. A semiconductor device comprising:

a substrate;

a wiring layer formed over said substrate; and

first, second, third, fourth, fifth, sixth, seventh, and eighth electrode structures arranged in order in said wiring layer;

wherein said first and fifth electrode structures are connected to each other with a first conductive line having a first node, said second and sixth electrode structures are connected to each other with a second conductive line having a second node, said third and seventh electrode structures are connected to each other with a third conductive line having a third node, said fourth and eighth electrode structures are connected to each other with a fourth conductive line having a fourth node, and

wherein a first voltage is applied to said first node, a second voltage that is lower than said first voltage is applied to said second node, a third voltage is applied to said third node, and a fourth voltage that is higher than said third voltage is applied to said fourth node, the first, second, third, and fourth voltages being independently applied.

2. The semiconductor device as set forth in claim 1 , wherein said first, second, third, fourth, fifth, sixth, seventh, and eighth electrode structures are arranged in parallel with each other.

3. The semiconductor device as set forth in claim 2 , wherein said first, second, third, fourth, fifth, sixth, seventh, and eighth electrode structures are arranged at regular intervals.

4. A semiconductor device comprising:

a substrate;

a wiring layer formed over said substrate; and

first, second, third, fourth, fifth, sixth, seventh, and eighth electrode structures arranged in order in said wiring layer;

wherein said first and fifth electrode structures are connected to each other with a first conductive line having a first node, said second and sixth electrode structures are connected to each other with a second conductive line having a second node, said third and seventh electrode structures are connected to each other with a third conductive line having a third node, said fourth and eighth electrode structures are connected to each other with a fourth conductive line having a fourth node, and

wherein a first voltage is applied to said first node, a second voltage that is higher than said first voltage is applied to said second node, a third voltage is applied to said third node, and a fourth voltage that is lower than said third voltage is applied to said fourth node, the first, second, third, and fourth voltages being independently applied.

5. The semiconductor device as set forth in claim 4 , wherein said first, second, third, fourth, fifth, sixth, seventh, and eighth electrode structures are arranged in parallel with each other.

6. The semiconductor device as set forth in claim 5 , wherein said first, second, third, fourth, fifth, sixth, seventh, and eighth electrode structures are arranged at regular intervals.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2012
From: FURUMIYA, MASAYUKI; KIKUTA, KUNIKO; YAMAMOTO, RYOTA; NAKAYAMA, MAKOTO
To: NEC ELECTRONICS CORPORATION
Reel/Frame 029435/0528 →
CHANGE OF NAME Recorded Dec 10, 2012
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 029435/0660 →
Priority Claims (1)
JP 2004-307664 · Oct 22, 2004 · national
Continuity (3)
Continuation 12707121 · Feb 17, 2010
Division 11247296 · Oct 12, 2005
Related Publication 20110254130A1 · Oct 20, 2011