System and method for estimating and correcting phase shift in a wireless communication device

1. A wireless communication element, comprising:

a transmit path configured to convert a digital signal output by digital circuitry into a wireless communication signal, the transmit path comprising a phase compensator configured to, based on a calculated phase error, convert the digital signal into a compensated digital signal, such that the transmit path may convert the compensated digital signal into the wireless communication signal; and

a phase error estimation path communicatively coupled to the transmit path and configured to calculate the calculated phase error based on a difference between an estimated instantaneous reference phase of the digital signal output by the digital circuitry and an estimated transmit phase of the wireless communication signal;

a summer configured to calculate a single-sample phase error equal to a difference between the estimated instantaneous reference phase and the estimated transmit phase;

a phase error averager configured to calculate an averaged phase error based on a given number of samples of the single-sample phase error; and

a phase compensation table configured to:

store the averaged phase error average as an entry in the table corresponding to a present output power of the transmit path; and

communicate a signal indicative of the value of the entry in the table corresponding to the present output power;

wherein the transmit path is configured to select the value of the entry in the table corresponding to the present output power as the calculated phase error.

2. A wireless communication element according to claim 1 , the phase error estimation path comprising:

an instantaneous reference phase estimator configured to calculate the estimated instantaneous reference phase based on in-phase and quadrature components of the digital signal output by the digital circuitry; and

a transmit phase estimator configured to calculate the estimated transmit phase based on in-phase and quadrature components of the wireless communication signal.

3. A wireless communication element according to claim 1 , the phase error estimation path further comprising a phase error limiter configured to limit the averaged phase error to at least one of an upper bound and a lower bound based on at least one of a given limit threshold and in-phase and quadrature components of the digital signal output by the digital circuitry.

4. A wireless communication element according to claim 1 , the phase error estimation path further comprising a delay element configured to delay the digital signal output by the digital circuitry such that the delayed signal is delayed from digital signal the time delay approximately equal to a signal delay of the transmit path.

5. A wireless communication element according to claim 1 , wherein the transmit path is configured to select between the single-sample phase error and the value of the entry in the table corresponding to the present output power as the calculated phase error.

6. A wireless communication element according to claim 1 , wherein the estimated instantaneous reference phase of the digital signal is based on a delayed signal having a time delay from the digital signal approximately equal to a signal delay of the transmit path.

7. A method for estimating and correcting phase shift in a wireless communication device, comprising:

converting a digital signal output by digital circuitry of the wireless communication device into a compensated digital signal based on a calculated phase error;

converting the compensated digital signal into a wireless communication signal;

calculating an estimated instantaneous reference phase of the digital signal output by the digital circuitry based on the delayed signal;

calculating an estimated transmit phase of the wireless communication signal;

calculating a phase error based on a difference between the estimated instantaneous reference phase and the estimated transmit phase of the wireless communication signal;

calculating a single-sample phase error equal to the difference between the estimated instantaneous reference phase and the estimated transmit phase;

calculating an averaged phase error based on a given number of samples of the single-sample phase error;

storing the averaged phase error average as an entry in a phase compensation table, the entry corresponding to a present output power of the wireless communication signal;

communicating a signal indicative of the value of the entry in the table corresponding to the present output power; and

selecting the value of the entry in the table corresponding to the present output power as the calculated phase error.

8. A method according to claim 7 , wherein calculating the estimated instantaneous reference phase includes calculating a phase based on in-phase and quadrature components of the digital signal output by the digital circuitry.

9. A method according to claim 7 , wherein calculating the estimated transmit phase includes calculating a phase based on in-phase and quadrature components of the wireless communication signal.

10. A method according to claim 7 , further comprising selecting between the value of the entry in the table corresponding to the present output power and the single-sample phase error as the calculated phase error.

11. A method according to claim 7 , further comprising limiting the averaged phase error to at least one of an upper bound and a lower bound based on at least one of a given limit threshold and in-phase and quadrature components of the digital signal output by the digital circuitry.

12. A method according to claim 7 , further comprising delaying the digital signal output by the digital circuitry such that the delayed signal is delayed from the digital signal a time delay approximately equal to a signal delay of a transmission path.

13. Non-transitory computer readable memory including logic operable, when executed, to:

convert a digital signal output by digital circuitry of a wireless communication device into a compensated digital signal based on a calculated phase error;

convert the compensated digital signal into a wireless communication signal;

calculate an estimated instantaneous reference phase of the digital signal output by the digital circuitry based on the delayed signal;

calculate an estimated transmit phase of the wireless communication signal; and

calculate a phase error based on a difference between the estimated instantaneous reference phase and the estimated transmit phase of the wireless communication signal;

calculate a single-sample phase error equal to the difference between the estimated instantaneous reference phase and the estimated transmit phase;

calculate an averaged phase error based on a given number of samples of the single-sample phase error;

store the averaged phase error average as an entry in a phase compensation table, the entry corresponding to a present output power of the wireless communication signal;

communicate a signal indicative of the value of the entry in the table corresponding to the present output power; and

select the value of the entry in the table corresponding to the present output power as the calculated phase error.

14. The non-transitory computer readable memory of claim 13 , wherein calculating the estimated instantaneous reference phase comprises calculating a phase based on in-phase and quadrature components of the digital signal output by the digital circuitry.

15. The non-transitory computer readable memory of claim 13 , wherein calculating the estimated transmit phase comprises calculating a phase based on in-phase and quadrature components of the wireless communication signal.

16. The non-transitory computer readable memory of claim 13 , wherein the logic is further operable, when executed, to select between the value of the entry in the table corresponding to the present output power and the single-sample phase error as the calculated phase error.

17. The non-transitory computer readable memory of claim 13 , wherein the logic is further operable, when executed, to limit the averaged phase error to at least one of an upper bound and a lower bound based on at least one of a given limit threshold and in-phase and quadrature components of the digital signal output by the digital circuitry.

18. The non-transitory computer readable memory of claim 13 , wherein the logic is further operable, when executed, to delay the digital signal output by the digital circuitry such that the delayed signal is delayed from the digital signal a time delay approximately equal to a signal delay of a transmission path.