IP Library Granted Patent US 8,725,933
Granted Patent B2
US 8,725,933 · App. 13/175,534 · Granted May 13, 2014

Method to detect uncompressible data in mass storage device

Inventor: Jawad B. Khan (Cornelius, OR)
Assignee: Intel Corporation
G06F12/0246G06F2212/401H03M7/6082
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,725,933
App. No.
13/175,534
Granted
May 13, 2014
Kind
B2
Abstract

Described are embodiments of methods, apparatus, and systems for detecting incompressible data and selectively compressing compressible data without compressing the incompressible data. A method may include determining a first compressibility value of first data of a plurality of input data and a second compressibility value of second data of the plurality of input data, determining that the first data is incompressible based at least in part on the first compressibility value relative to a compressibility threshold, and compressing the second data of the plurality of input data. Other embodiments may be described and claimed.

Claims (31)

1. A method comprising:

determining, by a computing device, a first compressibility value of first data of a plurality of input data and a second compressibility value of second data of the plurality of input data;

determining, by the computing device, that the first data is incompressible based at least in part on the first compressibility value relative to a compressibility threshold; and

compressing, by the computing device, the second data of the plurality of input data,

wherein the determining the first compressibility value comprises determining a first arithmetic average of non-zero frequencies of data units among the first data of the plurality of input data, and determining the second compressibility value comprises determining a second arithmetic average of non-zero frequencies of data units among the second data of the plurality of input data.

2. The method of claim 1 , further comprising, after compressing the second data, writing the first data and the second data to a solid-state memory device.

3. The method of claim 2 , wherein the solid-state memory device comprises NAND flash memory or phase-change memory.

4. The method of claim 2 , wherein the writing the first data comprises, after compressing the second data, writing the first data to the solid-state memory device without compressing the first data.

5. The method of claim 1 , wherein the determining that the first data is incompressible comprises comparing the first compressibility value of the first data to the compressibility threshold.

6. The method of claim 1 , wherein the determining the first compressibility value and the second compressibility value further comprises:

assigning the first compressibility value to the first data based at least in part on the first average; and

assigning the second compressibility value to the second data based at least in part on the second average.

7. An apparatus comprising:

an incompressibility detection module configured to determine a first compressibility value of first data of a plurality of input data and a second compressibility value of second data of the plurality of input data, and determine that the first data is incompressible based at least in part on the first compressibility value relative to a compressibility threshold; and

a compression module operatively coupled to the incompressibility detection module and configured to compress the second data of the plurality of input data,

wherein the incompressibility detection module is configured to determine the first compressibility value based at least in part on a first arithmetic average of non-zero frequencies of data units among the first data of the plurality of input data, and the second compressibility value based at least in part on a second arithmetic average of non-zero frequencies of data units among the second data of the plurality of input data.

8. The apparatus of claim 7 , further comprising write circuitry configured to write the first data and the compressed second data to a solid-state memory device.

9. The apparatus of claim 8 , wherein the compression module is configured to provide the first data to the write circuitry without compressing the first data.

10. The apparatus of claim 7 , further comprising a solid-state memory device comprising NAND flash memory or phase-change memory.

11. The apparatus of claim 10 , further comprising a memory controller, wherein the incompressibility detection module is operatively coupled between the memory controller and the solid-state memory device.

12. The apparatus of claim 7 , wherein the incompressibility detection module is configured to determine that the first data is incompressible by comparing the first compressibility value of the first data to the compressibility threshold.

13. The apparatus of claim 7 , further comprising a hash table, wherein the incompressibility detection module is configured to track instances of the data units among the first or second data in the hash table.

14. A system comprising:

a memory apparatus including:

an incompressibility detection module configured to determine a first compressibility value of first data of a plurality of input data and a second compressibility value of second data of the plurality of input data, and determine that the first data is incompressible based at least in part on the first compressibility value relative to a compressibility threshold, wherein the incompressibility detection module is configured to determine the first compressibility value based at least in part on a first arithmetic average of non-zero frequencies of data units among the first data of the plurality of input data, and the second compressibility value based at least in part on a second arithmetic average of non-zero frequencies of data units among the second data of the plurality of input data; and

a compression module operatively coupled to the incompressibility detection module and configured to compress the second data of the plurality of input data;

a bus operatively coupled to the memory apparatus; and

a display device operatively coupled to the bus.

15. The system of claim 14 , further comprising a memory controller, wherein the memory controller includes the incompressibility detection module and the compression module.

16. The system of claim 14 , wherein the system is a selected one of a desktop computer, a laptop computer, a handheld computer, a tablet computer, a netbook computer, a server, a set-top box, a digital recorder, a game console, a smart phone, a personal digital assistant, a mobile phone, a digital media player, or a digital camera.

17. The system of claim 14 , further comprising one or more antennae and configured to establish a wireless communication link with one or more components of a wireless network.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2014
From: KHAN, JAWAD B.
To: INTEL CORPORATION
Reel/Frame 032186/0861 →
Continuity (1)
Related Publication 20130007346A1 · Jan 3, 2013