Reduction of electrostatic coupling for a thyristor-based memory cell
View Patent ↗Embodiments of integrated circuits for mitigating against electrostatic coupling are described. In an embodiment, first gate dielectrics are respectively located over first active regions. First isolation regions are respectively located between the first active regions. Second gate dielectrics are respectively located over second active regions. Second isolation regions are respectively located between the second active regions. In an embodiment, the first active regions are approximately 20 to 80 percent shorter in height/thickness than the second active regions. In another embodiment, the first isolation regions extend above an uppermost surface of the first gate dielectrics while providing gaps between the first isolation regions and sidewalls of the first active regions for receipt of material used in formation of conductive lines. In yet another embodiment, active area stripes are narrower in width at p-base regions and n-base regions than at cathode regions and anode regions respectively thereof.
1. An integrated circuit for mitigating against electrostatic coupling, comprising:
thyristor-based memory cells formed with spaced-apart active area stripes; and
each of the thyristor-based memory cells having a p-base region, an n-base region, a cathode region, and an anode region respectively associated with each of the active area stripes to provide p-base regions, n-base regions, cathode regions, and anode regions;
wherein the active area stripes are narrower in width at the p-base regions and the n-base regions respectively thereof than at the cathode regions and the anode regions respectively thereof.
2. The integrated circuit according to claim 1 , wherein width of the active area stripes at the p-base regions and the n-base regions respectively thereof is less than approximately 0.5 multiplied by pitch of the active area stripes.
3. The integrated circuit according to claim 2 , wherein the pitch is a lithographic minimum active-to-active spacing.
4. The integrated circuit according to claim 2 , wherein the active area stripes are defined in a bulk silicon wafer.
5. The integrated circuit according to claim 2 , wherein the active area stripes are defined in a semiconductive layer of a semiconductor-on-insulator wafer.