Power semiconductor devices, structures, and related methods
View Patent ↗Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
1. A semiconductor device, comprising:
a first-conductivity-type semiconductor source region;
a second-conductivity-type semiconductor body region;
a gate electrode, which is capacitively coupled to invert a portion of said body region, to thereby create a channel;
a semiconductor drift region which includes both first-conductivity-type and second-conductivity-type semiconductor portions in parallel;
immobile electrostatic charge which is capacitively coupled to invert parts of said second-conductivity-type drift region portions; and
a first-conductivity-type semiconductor drain region;
wherein said body region is interposed between said source region and said drift region;
and wherein said drift region is interposed between said body region and said drain region;
and further comprising an intermediate layer which has a first conductivity type, and has a higher doping than said first-conductivity-type semiconductor portion, and which electrically connects said channel both laterally and vertically to both said first-conductivity-type and said second-conductivity-type semiconductor portions, and which is physically interposed between said channel and both said first-conductivity-type and said second-conductivity-type semiconductor portions;
whereby, in the ON state, majority carriers flow both through said first-conductivity-type portions, and at least some parts of said second-conductivity-type portions of said drift region, in parallel.
2. The device of claim 1 , wherein said first-conductivity-type source region is n-type, and said majority carriers are electrons.
3. The device of claim 1 , wherein said source, body, intermediate, and drain regions are silicon.
4. The device of claim 1 , wherein said immobile electrostatic charge is provided by cesium ions.
5. The device of claim 1 , wherein said immobile electrostatic charge consists of point charges.
6. The device of claim 1 , wherein said immobile electrostatic charge is provided by ions in dielectric material and/or by ions at a dielectric/semiconductor interface.
7. The device of claim 1 , wherein said gate electrode lies entirely inside a trench.
8. The device of claim 1 , wherein said immobile electrostatic charge is provided by ions in dielectric material in a trench.
9. The device of claim 8 , wherein said trench includes a void.
10. A semiconductor device, comprising:
an n-type semiconductor source region;
a p-type semiconductor body region;
a gate electrode, which is capacitively coupled to invert a portion of said body region, to thereby create a channel;
a semiconductor drift region which includes both n-type and p-type semiconductor portions electrically connected in parallel;
immobile positive ions which are capacitively coupled to jointly invert parts of said p-type drift region portions; and
an n-type semiconductor drain region;
wherein said body region is interposed between said source region and said drift region;
and wherein said drift region is interposed between said body region and said drain region;
and further comprising an n-type intermediate layer which has a higher doping than said n-type semiconductor portion of said drift region, and which electrically connects said channel both laterally and vertically to both said n-type and said p-type semiconductor portions, and which is physically interposed between said channel and both said n-type and said p-type semiconductor portions;
whereby, in the ON state, electrons flow both through said n-type portions and said p-type portions of said drift region in parallel.
11. The device of claim 10 , wherein said source, body, drain and drift regions are silicon.
12. The device of claim 10 , wherein said immobile positive ions are cesium ions.
13. The device of claim 10 , wherein said gate electrode lies entirely inside a trench.
14. A semiconductor device, comprising:
a first-conductivity-type semiconductor source region;
a second-conductivity-type semiconductor body region;
a gate electrode, which is capacitively coupled to invert a portion of said body region, to thereby create a channel;
a semiconductor drift region which includes both first-conductivity-type and second-conductivity-type semiconductor portions in parallel;
immobile electrostatic charge which is capacitively coupled to invert parts of said second-conductivity-type drift region portions; and
a first-conductivity-type semiconductor drain region;
wherein said body region is interposed between said source region and said drift region;
and wherein said drift region is interposed between said body region and said drain region;
whereby, in the ON state, majority carriers flow both through said first-conductivity-type portions and said second-conductivity-type portions of said drift region in parallel;
wherein said gate electrode lies in a first trench; and wherein said immobile electrostatic charge lies in one or more second trenches; and wherein said first trench has a different depth than said one or more second trenches.
15. The device of claim 14 , wherein said first-conductivity-type source region is n-type, and said majority carriers are electrons.
16. The device of claim 14 , wherein said source, body, drain and drift regions are silicon.
17. The device of claim 14 , wherein said immobile electrostatic charge is provided by cesium ions.
18. The device of claim 14 , wherein said immobile electrostatic charge consists of point charges.
19. The device of claim 14 , wherein said immobile electrostatic charge is provided by ions in dielectric material and/or by ions at a dielectric/semiconductor interface.
20. The device of claim 14 , wherein said gate electrode lies entirely inside a trench.
21. The device of claim 14 , wherein said immobile electrostatic charge is provided by ions in dielectric material in a trench.
22. The device of claim 21 , wherein said trench includes a void.