Power supply interconnect structure of semiconductor integrated circuit
View Patent ↗A power supply interconnect structure of a semiconductor integrated circuit includes a single borderless stack via electrically connecting power supply interconnects of two different interconnect layers to form a connecting portion of the interconnects, and a multi-stack via functioning as another connecting portion of the interconnects, which electrically connect the power supply interconnects, and having a wide pad portion. The single borderless stack via is located in an interconnect region with high signal interconnect density. The multi-stack via is located in an interconnect region with low signal interconnect density. This increases interconnection efficiency in the region with the high signal interconnect density to improve interconnection characteristics. This enables reduction in an area of a chip and increases compatibility to an EDA tool, thereby improving IR-DROP characteristics.
1. A power supply interconnect structure of a semiconductor integrated circuit comprising:
power supply interconnects located in two different interconnect layers with at least one single intermediate interconnect layer interposed between the different interconnect layers; and
a single borderless stack via electrically connecting the power supply interconnects located in the two interconnect layers to form a connecting portion of the interconnects,
wherein the single borderless stack via forming the connecting portion of the interconnects includes:
single vias located in respective two or more insulating layers located between the two interconnect layers, and
an interconnect located in each of the at least one intermediate interconnect layer, and having a same cross-sectional shape as the single vias of the insulating layers, and
the single vias of the insulating layers and the interconnect of the at least one intermediate interconnect layer are alternately layered in a same vertical line and electrically connected to form a unit.
2. The power supply interconnect structure of claim 1 , wherein the unit of the single borderless stack via includes:
single vias located in respective three insulating layers, and
interconnects located in respective two intermediate interconnect layers interposed between the three insulating layers.
3. The power supply interconnect structure of claim 1 , wherein multiples ones of the unit of the single borderless stack via are formed, and distances between the units are equal.
4. The power supply interconnect structure of claim 1 , wherein multiple ones of the unit of the single borderless stack via are formed, and distances between the units are equal and unequal.
5. The power supply interconnect structure of claim 1 , wherein multiple ones of the unit of the single borderless stack via are formed, and a first signal interconnect is located in a region between two adjacent ones of the units.
6. The power supply interconnect structure of claim 5 , wherein a distance between the single borderless stack via and the first signal interconnect is equal to a distance between the first signal interconnect and a second signal interconnect adjacent to the first signal interconnect.
7. A power supply interconnect structure of a semiconductor integrated circuit comprising:
power supply interconnects located in two different interconnect layers with at least one single intermediate interconnect layer interposed between the different interconnect layers; and
a single borderless stack via electrically connecting the power supply interconnects located in the two interconnect layers to form a connecting portion of the interconnects, the single borderless stack via forming the connecting portion of the interconnects; and
a multi-stack via configured to electrically connect the power supply interconnects located in the two interconnect layers to form another connecting portion of the interconnects.
8. The power supply interconnect structure of claim 7 , wherein the multi-stack via includes:
a plurality of vias located in respective two or more insulating layers located between the two interconnect layers, and
an interconnect located in each of the at least one intermediate interconnect layer and having a pad portion to include the plurality of vias in the two or more insulating layers inside when viewed from above, and
the plurality of vias of the insulating layers and the interconnect of the at least one intermediate interconnect layer are alternately layered in a same vertical line and electrically connected.
9. The power supply interconnect structure of claim 7 , wherein the single borderless stack via forming the connecting portion of the interconnects is located in a signal interconnect region, and the multi-stack via forming the other connecting portion of the interconnects is located in a non-interconnect region to which a signal is not interconnected.
10. The power supply interconnect structure of claim 7 , wherein
the multi-stack via forming the other connecting portion of the interconnects is located in a region of the signal interconnect region having predetermined signal interconnect density, and
the single borderless stack via forming the connecting portion of the interconnects is located in an interconnect region of the signal interconnect region, which has signal interconnect density higher than the predetermined density.
11. The power supply interconnect structure of claim 9 , wherein multiple ones of the single borderless stack via are located in a plurality of places, and a distance between the multiple ones of the single borderless stack via is longer than a distance between the plurality of vias in a same insulating layer of the multi-stack via.
12. The power supply interconnect structure of claim 1 , further comprising:
the single borderless stack via forming the connecting portion of the interconnects; and
a multi-stack via configured to electrically connect the power supply interconnects located in the two interconnect layers to form another connecting portion of the interconnects.
13. The power supply interconnect structure of claim 12 , wherein the unit of the single borderless stack via includes:
single vias located in respective three insulating layers, and
interconnects located in respective two intermediate interconnect layers interposed between the three insulating layers.
14. The power supply interconnect structure of claim 12 , wherein multiples ones of the unit of the single borderless stack via are formed, and distances between the units are equal.
15. The power supply interconnect structure of claim 12 , wherein multiple ones of the unit of the single borderless stack via are formed, and distances between the units are equal and unequal.
16. The power supply interconnect structure of claim 12 , wherein multiple ones of the unit of the single borderless stack via are formed, and a first signal interconnect is located in a region between two adjacent ones of the units.
17. The power supply interconnect structure of claim 16 , wherein a distance between the single borderless stack via and the first signal interconnect is equal to a distance between the first signal interconnect and a second signal interconnect adjacent to the first signal interconnect.