Fin FET and method of fabricating same
View Patent ↗A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.
1. A structure of a field effect transistor comprising:
an active region and a device isolation film;
a first recess in the device isolation film having a first gate electrode disposed therein, the first recess having a first depth measured from an uppermost surface of the active region;
a second recess in the active region having a second gate electrode disposed therein, the second recess having a second depth measured from the uppermost surface of the active region, the second depth being less than the first depth;
a gate insulation layer disposed between the active region and the second gate electrode; and
source/drain regions disposed in the active region on both sides of the second gate electrode.
2. The structure of claim 1 , wherein a portion of the active region protrudes above the device isolation film.
3. The structure of claim 2 , wherein the uppermost surface of the active region extends about 1000 Å to 1500 Å above an uppermost surface of the device isolation film.
4. The structure of claim 2 , wherein an upper edge portion of the active region is curved.
5. The structure of claim 2 , wherein a bottom surface of the second gate electrode is curved and is located below the uppermost surface of the active region.
6. The structure of claim 1 , wherein a difference between the first depth and the second depth is about 700 Å.
7. The structure of claim 1 , wherein the second gate electrode comprises a first gate conduction layer disposed on the gate insulation layer in the second recess and a second gate conduction layer disposed on the first gate conduction layer.
8. The structure of claim 7 , wherein the first conduction layer comprises a poly-silicon and the second conduction layer comprise a tungsten (W).
9. The structure of claim 1 , wherein the second gate electrode disposed in the second recess extends above the uppermost surface of the active region.
10. The structure of claim 1 , wherein the gate insulation layer is disposed in the second recess.
11. A memory cell device comprising:
a field effect transistor comprising:
an active region and a device isolation film;
a first recess in the device isolation film having a first gate electrode disposed therein, the first recess having a first depth measured from an uppermost surface of the active region;
a second recess in the active region having a second gate electrode disposed therein, the second recess having a second depth measured from the uppermost surface of the active region, the second depth being less than the first depth;
a gate insulation layer disposed between the active region and the second gate electrode;
source/drain regions disposed in the active region on both sides of the second gate electrode; and
a capacitor connected to the field effect transistor.
12. The device of claim 11 , wherein a portion of the active region protrudes above the device isolation film.
13. The device of claim 12 , wherein the uppermost surface of the active region extends about 1000 Å to 1500 Å above an uppermost surface of the device isolation film.
14. The device of claim 12 , wherein an upper edge portion of the active region is curved.
15. The device of claim 12 , wherein a bottom surface of the second gate electrode is curved and is located below the uppermost surface of the active region.
16. The device of claim 11 , wherein a difference between the first depth and the second depth is about 700 Å.
17. The device of claim 11 , wherein the second gate electrode comprises a first gate conduction layer disposed on the gate insulation layer in the second recess and a second gate conduction layer disposed on the first gate conduction layer.
18. The device of claim 17 , wherein the first conduction layer comprises a poly-silicon and the second conduction layer comprises a tungsten (W).
19. The device of claim 11 , wherein the second gate electrode disposed in the second recess extends above the uppermost surface of the active region.
20. The device of claim 11 , wherein the gate insulation layer is disposed in the second recess.
21. A semiconductor device comprising:
an active region and a device isolation film;
a first recess in the device isolation film having a first gate electrode disposed therein, the first recess having a first depth measured from an uppermost surface of the active region;
a second recess in the active region having a second gate electrode disposed therein, the second recess having a second depth measured from the uppermost surface of the active region, the second depth being less than the first depth;
a third recess in the active region having a third gate electrode disposed therein, the third recess having the second depth measured from the uppermost surface of the active region;
a first gate insulator disposed between the active region and the second gate electrode, the first gate insulator disposed in the second recess; and
a second gate insulator disposed between the active region and the third gate electrode, the second gate insulator disposed in the third recess,
wherein the second gate electrode is a gate electrode of a first transistor formed at the active region and the third gate electrode is a gate electrode of a second transistor disposed adjacent to the first transistor at the active region, and the device further comprises,
a shared drain region disposed in the active region between the second gate electrode and the third gate electrode;
a first source region disposed in the active region at a side of the second gate electrode opposite the shared drain region; and
a second source region disposed in the active region at a side of the third gate electrode opposite the shared drain region.
22. The device of claim 21 , wherein a portion of the active region protrudes above the device isolation film.
23. The device of claim 22 , wherein the uppermost surface of the active region extends about 1000 Å to 1500 Å above an uppermost surface of the device isolation film.
24. The device of claim 22 , wherein an upper edge portion of the active region is curved.
25. The device of claim 22 , wherein bottom surfaces of the second and third gate electrodes are curved and are located below the uppermost surface of the active region.
26. The device of claim 21 , wherein a difference between the first depth and the second depth is about 700 Å.
27. The device of claim 21 , wherein each of the second gate electrode and third gate electrode comprises a first gate conduction layer disposed on the corresponding gate insulator and a second gate conduction layer disposed on the first gate conduction layer.
28. The device of claim 27 , wherein the first conduction layer of each of the second and third gate electrodes comprises a poly-silicon and the second conduction layer comprises a tungsten (W).
29. The device of claim 21 , wherein each of the second gate electrode and third gate electrode extends above the uppermost surface of the active region.