Semiconductor device with isolation trench liner
A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
1. A semiconductor device comprising:
a layer of semiconductor material having an active transistor region defined therein;
an isolation trench formed in the layer of semiconductor material adjacent to the active transistor region;
a trench liner lining the isolation trench, wherein the isolation trench and the trench liner together form a lined trench;
an insulating material in the lined trench; and
a layer of high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, the layer of high-k gate material being divided by the trench liner such that the trench liner separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.
2. The semiconductor device of claim 1 , wherein:
the trench liner comprises a material that substantially inhibits nucleation of high-k material thereon; and
the layer of high-k gate material is formed by deposition over the insulating material and over the active transistor region.
3. The semiconductor device of claim 1 , wherein the trench liner forms an oxygen barrier between the high-k gate material overlying the portion of the insulating material and the high-k gate material overlying the portion of the active transistor region.
4. The semiconductor device of claim 1 , wherein:
the trench liner includes an upper rim; and
the upper rim is substantially void of the high-k gate material.
5. The semiconductor device of claim 1 , further comprising:
a metal gate layer overlying the high-k gate material and overlying the trench liner; and
a polysilicon gate layer overlying the metal gate layer.
6. The semiconductor device of claim 1 , wherein the trench liner is formed from a nitride material.
7. The semiconductor device of claim 1 , wherein the insulating material is an oxide material.