IP Library Granted Patent US 8,847,619
Granted Patent B2
US 8,847,619 · App. 13/179,247 · Granted Sep 30, 2014

Apparatus and methods for through substrate via test

Inventors: Ebrahim H Hargan (Boise, ID); Layne Bunker (Boise, ID); Dragos Dimitriu (Boise, ID); Gregory King (Hastings, MN)
Assignee: Micron Technology, Inc.
H01L22/22G11C2029/5006H01L2924/014H01L22/14G11C29/816G11C29/025G11C29/02G01R31/2853G11C29/022
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Quick Facts
Patent No.
US 8,847,619
App. No.
13/179,247
Granted
Sep 30, 2014
Kind
B2
Abstract

A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

Claims (12)

1. A method of testing a stack of interconnected electronic devices, comprising:

comparing a voltage drop caused by imposition of a repeating signal from a ring oscillator circuit and a current from a current source across a termination resistor and a sum of a resistance formed by a series connected electrical path between an input/output connection on one of a plurality of electronic devices included in the stack and an input/output connection on another one of the plurality of electronic devices included in the stack to determine a quality of the series connected electrical path in the stack, wherein the ring oscillator circuit forms a part of one of the plurality of electronic devices.

2. The method of claim 1 , wherein the comparing is repeated after the plurality of electronic devices is exposed to at least one of a function test, a static bias test, an environmental stress, or an accelerated aging test for a selected period of time.

3. The method of claim 2 , wherein the comparing is repeated to determine at least one of an aging rate or a failure rate.

4. The method of claim 3 , wherein at least one of a value of the termination resistor and a termination voltage are varied prior to the comparing.

5. The method of claim 1 , further comprising:

comparing a voltage drop in a first one of the plurality of electronic devices while the remaining ones of the plurality of electronic devices are in an un-powered state.

6. A method for testing a stack of a plurality of interconnected electronic devices, comprising:

comparing a voltage drop, caused by imposition of a repeating signal from a ring oscillator circuit that forms a part of one of the plurality of electronic devices, across a first termination resistor and a sum of a resistance formed by a first series connected electrical path between an input/output connection on one of the plurality of electronic devices and a second termination resistor and a second series connected electrical path between an input/output connection on another one of the plurality of electronic devices to determine a quality of each of the first and second series connected electrical paths.

7. The method of claim 6 further comprising comparing a measured (RC) delay between the first and second series connected electrical paths to determine the quality of each of the first and second series connected electrical paths.

8. The method of claim 7 further comprising replacing one of the first or the second series connected electrical paths with a redundant series connected electrical path in response to the quality.

9. The method of claim 6 wherein the signal from the oscillator is a repeating clock signal.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2014
From: HARGAN, EBRAHIM H; BUNKER, LAYNE; DIMITRIU, DRAGOS; KING, GREGORY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 033430/0680 →
Continuity (2)
Division 12173722 · Jul 15, 2008
Related Publication 20110267092A1 · Nov 3, 2011