IP Library Patent Application 13181935
Patent Application
App. No. 13/181,935

CRYOGENIC SILICON ION-IMPLANTATION AND RECRYSTALLIZATION ANNEALING

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Patent No.
US None
App. No.
13/181,935
Abstract

Described herein are methods for forming a semiconductor structure. The methods involve forming a doped semiconductor film, amorphizing the doped semiconductor film through ion implantation; and annealing the doped semiconductor film. The ion implantation and the annealing can increase an activation efficiency of the dopant. The ion implantation and the annealing can also reduce a number of crystalline defects in the doped semiconductor film.

Claims (28)

1 . A method for increasing dopant activation efficiency in a doped silicon film, comprising:

forming a doped silicon film with a peak dopant concentration of 1×10 20 cm −3 or more;

amorphizing the doped silicon film through ion implantation; and

annealing the doped silicon film.

2 . The method of claim 1 , wherein forming the doped silicon film comprises an epitaxial growth process.

3 . The method of claim 1 , wherein forming the doped silicon film comprises a vapor phase epitaxial growth process.

4 . The method of claim 3 , wherein forming the doped silicon film comprises using a gas with a mixture of SiH 2 Cl 2 /H 2 in the vapor phase epitaxial growth process.

5 . The method of claim 1 , wherein forming the doped silicon film comprises using at least one of boron, arsenic or phosphorous as a dopant.

6 . The method of claim 1 , wherein the amorphizing comprises ion implantation at a temperature of about −60 degrees Celsius or lower.

7 . The method of claim 1 , wherein annealing the doped silicon film is conducted at a temperature from about 1100 degrees Celsius or more to about 1300 degrees Celsius or less.

8 . The method of claim 1 , wherein annealing the doped silicon film is conducted for a time period of about 10 milliseconds or less.

9 . The method of claim 1 , wherein annealing the doped silicon film is conducted for a time period of about 2 milliseconds or less.

10 . A method of making a source/drain structure for a transistor, comprising:

forming a doped silicon film with a peak dopant concentration of 1×10 20 cm −3 or more using an epitaxial growth process;

implanting silicon ions in the doped silicon film at a temperature of about 0 degrees Celsius or less; and

annealing the doped silicon film for a time period of about two milliseconds or less.

11 . The method of claim 10 , wherein implanting silicon ions in the doped silicon film is conducted at a temperature of about −60 degrees Celsius or less.

12 . The method of claim 10 , wherein forming the doped silicon film comprises using at least one of arsenic, boron or phosphorous.

13 . The method of claim 10 , wherein forming the doped silicon film is conducted at a temperature of about 600 degrees Celsius or greater.

14 . The method of claim 10 , wherein annealing the doped silicon film is conducted at a temperature of about 1100 degrees Celsius or greater and about 1300 degrees Celsius or less.

15 . The method of claim 10 , wherein annealing comprises at least one of nonmelt laser annealing or flash lamp annealing.

16 . A method for reducing crystal defects in a doped silicon epitaxial film, comprising:

performing silicon ion implantation on the doped silicon epitaxial film at a temperature of about 0 degrees Celsius or less; and

annealing the doped silicon epitaxial film at a temperature of about 1100 degrees Celsius or more and about 1300 degrees Celsius or less for about 10 milliseconds or less.

17 . The method of claim 16 , further comprising annihilating defects in the doped silicon epitaxial film based on at least one of the performing the silicon ion implantation or the annealing.

18 . The method of claim 16 , wherein the doped silicon epitaxial film is a phosphorous doped silicon epitaxial film.

19 . The method of claim 16 , wherein annealing the doped silicon epitaxial film is conducted at a temperature from about 1200 degrees Celsius or more to about 1225 degrees Celsius or less.

20 . The method of claim 16 , wherein performing silicon ion implantation on the doped silicon epitaxial film is conducted at a temperature of about −60 degrees Celsius or less.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2012
From: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 027700/0242 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2011
From: ITOKAWA, HIROSHI
To: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Reel/Frame 026585/0156 →