Semiconductor device and test method thereof

1. A semiconductor device comprising:

a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of the dummy word lines is sandwiched between corresponding two of the word lines;

a main dummy word line electrically connected in common to the dummy word lines included in at least one of the memory mats; and

a dummy-word-line control circuit that detects an electric potential of the main dummy word line when a test signal is activated, and outputs an error signal when the electric potential exceeds a predetermined threshold value,

wherein the dummy-word-line control circuit brings the main dummy word line into a floating state when the test signal is activated.

2. The semiconductor device as claimed in claim 1 , wherein the dummy-word-line control circuit supplies a first electric potential to the main dummy word line when the test signal is inactivated.

3. The semiconductor device as claimed in claim 2 , further comprising a plurality of word line drivers, wherein

each of the word line drivers supplies a second electric potential to an associated one of the word lines when selecting and supplies the first electric potential to the associated one of the word lines when non-selecting.

4. The semiconductor device as claimed in claim 3 , wherein

the memory mats are arranged in a matrix in which a plurality of columns and a plurality of rows extend in first and second directions, respectively, and

at least a part of the main dummy word line extends in the first direction, and is commonly connected to the dummy word lines included in the memory mats that belong to at least one of the columns.

5. The semiconductor device as claimed in claim 4 , wherein the main dummy word line and the dummy-word-line control circuit are allocated to the memory mats that belong to more than one of the columns.

6. The semiconductor device as claimed in claim 5 , wherein

the main dummy word line includes a plurality of first main dummy word lines that extend in the first direction and a second main dummy word line that extends in the second direction,

each of the first main dummy word lines is commonly connected to the dummy word lines included in the memory mats that belong to an associated one of the columns,

the second main dummy word line is commonly connected to the first main dummy word lines, and

the dummy-word-line control circuit is connected to the first main dummy word lines via the second main dummy word line.

7. The semiconductor device as claimed in claim 4 , wherein the main dummy word line and the dummy-word-line control circuit are allocated to each of the columns.

8. The semiconductor device as claimed in claim 4 , wherein the word lines and the dummy word lines extend in the second direction and the bit lines extend in the first direction.

9. The semiconductor device as claimed in claim 8 , further comprising connecting wirings that connect the word lines and the word line drivers, wherein

the connecting wirings are formed in a first wiring layer that is different from a second wiring layer in which the part of the main dummy word line that extends in the first direction is formed.

10. The semiconductor device as claimed in claim 9 , wherein the first wiring layer is positioned between the second wiring layer and a wiring layer in which the word lines and the dummy word lines are formed.

11. A semiconductor device comprising:

a plurality of memory cells;

a plurality of word lines coupled to corresponding ones of the memory cells, the word lines elongating in parallel in a first direction;

a plurality of dummy word lines each arranged between corresponding two of the word lines, the dummy word lines elongating in parallel in the first direction;

a main dummy word line directly coupled, and in common, to the dummy word lines, the main dummy word line elongating in a second direction perpendicular to the first direction; and

a dummy word line control circuit physically connected to the main dummy word line and not physically contacting each of the dummy word lines, the dummy word line control circuit being configured to detect a potential of the main dummy word line.

12. The semiconductor device as claimed in claim 11 , wherein each of the dummy word lines is formed in a lower-level, the main dummy word line being formed in an upper-level, the semiconductor device further comprising a plurality of contact plugs each connecting the main dummy word line in the upper-level and a corresponding one of the dummy word lines in the lower-level.

13. The semiconductor device as claimed in claim 11 , wherein the dummy word line control circuit is configured to control a potential of the main dummy word line in response to a test signal.

14. The semiconductor device as claimed in claim 13 , wherein the dummy word line control circuit is configured to fix a potential of the main dummy word line when the test signal takes a first value.

15. The semiconductor device as claimed in claim 14 , wherein the dummy word line control circuit is configured to render the main dummy word line electrically floated when the test signal takes a second value.