System and method for controlling current to certain components of a wireless communication device

1. A wireless communication receiver, comprising:

a receive path configured to receive a wireless communication signal and convert the wireless communication signal into a digital signal based at least on an oscillator signal, the receive path comprising hardware including a downconverter, an analog-to-digital converter and an equalization filter located after the analog-to-digital converter in the receive path;

a control path communicatively coupled to the receive path and configured to: determine a signal strength of a signal in the receive path;

based at least on the signal strength, select a current mode from at least one of a first current mode and a second current mode for the wireless communication receiver, wherein the receive path has a first receive path gain and a first receive path delay in the first current mode and has a second receive path gain and a second receive path delay in the second current mode; and

communicate a control signal to the receive path indicative of the current mode;

the receive path configured to:

in response to the switch from the first current mode to the second current mode as indicated by the control signal, modify one or more operational parameters of the receive path such that the receive path consumes a lower amount of current than it does in the first current mode; and

in response to the switch from the second current mode to the first current mode as indicated by the control signal, modify one or more operational parameters of the receive path such that the receive path consumes a higher amount of current than it does in the second current mode; and

the equalization filter configured to, in response to a switch from the first current mode to the second current mode or a switch from the second current mode to the first current mode, modify a gain and a delay of the equalization filter to compensate for a gain difference between the first receive path gain associated with the first current mode and the second receive path gain associated with the second current mode, and to compensate for a delay difference between the first receive path delay associated with the first current mode and the second receive path delay associated with the second current mode.

2. The wireless communication receiver according to claim 1 , wherein modifying one or more operational parameters comprises modifying a bias current of one or more gain elements of the receive path.

3. The wireless communication receiver according to claim 1 , wherein modifying one or more operational parameters comprises modifying at least one of: a sampling rate of the analog-to-digital converter of the receive path, a coefficient of at least one feedback element of the analog-to-digital converter, and a gain element of the analog-to-digital converter.

4. The wireless communication receiver according to claim 3 , wherein modifying one or more operational parameters does not comprise modifying a topology of the analog-to-digital converter or modifying an order of the analog-to-digital converter.

5. The wireless communication receiver according to Claim 1 , wherein modifying one or more operational parameters comprises modifying at least one of: a sampling rate of a decimation filter of the receive path, a downsampling ratio of the decimation filter, and a coefficient of the decimation filter.

6. The wireless communication receiver according to claim 1 , the control path configured to select the first current mode if the signal strength is below a threshold signal strength.

7. The wireless communication receiver according to claim 1 , the control path configured to select the second current mode if the signal strength is above a threshold signal strength.

8. The wireless communication receiver according to claim 1 , wherein:

the analog-to-digital converter includes:

a plurality of integrators; and

a plurality of comparators, each of the plurality of comparators configured to compare an output of a respective integrator to a threshold to determine whether clipping is present at the output of the respective integrator; and

the control path is configured to select the current mode based further on whether clipping is present at one or more integrator outputs within the analog-to-digital converter.

9. A method comprising:

determining a signal strength of a signal in a receive path including an analog-to-digital converter and an equalization filter located after the analog-to-digital converter, of a wireless communication receiver, the receive path configured to receive a wireless communication signal and convert the wireless communication signal into a digital signal based at least on an oscillator signal;

based at least on the signal strength selecting a current mode from at least one of a first current mode and a second current mode for the wireless communication receiver;

communicating a control signal to the receive path indicative of the current mode; in response to the switch from the first current mode to the second current mode as indicated by the control signal, modifying one or more operational parameters of the receive path such that the receive path consumes a lower amount of current than it does in the first current mode;

in response to the switch from the second current mode to the first current mode as indicated by the control signal modifying one or more operational parameters of the receive path such that the receive path consumes a higher amount of current than it does in the second current mode;

wherein the receive path has a first receive path gain and a first receive path delay in the first current mode, and has a second receive path gain and a second receive path delay in the second current mode; and

in response to a switch from the first current mode to the second current mode or a switch from the second current mode to the first current mode, modifying a gain and a delay of the equalization filter associated with the receive path to compensate for a gain difference between the first receive path gain associated with the first current mode and the second receive path gain associated with the second current mode and to compensate for a delay difference between the first receive path delay associated with the first current mode and the second receive path delay associated with the second current mode.

10. A method according to claim 9 , wherein modifying one or more operational parameters comprises modifying a bias current of one or more gain elements of the receive path.

11. The method according to claim 9 , wherein modifying one or more operational parameters comprises modifying at least one of: a sampling rate of the analog-to-digital converter of the receive path, a coefficient of at least one feedback element of the analog-to-digital converter, and a gain element of the analog-to-digital converter.

12. The method according to claim 11 , wherein modifying one or more operational parameters does not comprise modifying a topology of the analog-to-digital converter or modifying an order of the analog-to-digital converter.

13. The method according to claim 9 , wherein modifying one or more operational parameters comprises modifying at least one of: a sampling rate of a decimation filter of the receive path, a downsampling ratio of the decimation filter, and a coefficient of the decimation filter.

14. The method according to claim 9 , further comprising selecting the first current mode if the signal strength is below a threshold signal strength.

15. The method according to claim 9 , further comprising selecting the second current mode if the signal strength is above a threshold signal strength.

16. The method according to claim 9 , further comprising:

comparing each of a plurality of integrator outputs within the analog-to-digital converter of the receive path to a threshold to determine whether clipping is present at one or more of the plurality of integrator outputs of the analog-to-digital converter; and

selecting the current mode based further on whether clipping is present at one or more of the plurality integrator outputs within the analog-to-digital converter.