Capacitors and methods of forming
Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate. A top contact may be formed laterally spaced from the trenched area by patterning laterally extended portions of one or more of the dielectric, polysilicon and top metal contact layers.
1. A method for forming a semiconductor device including a capacitor, comprising:
forming a trench pattern mask over a top of a semiconductor substrate including a doped region of given conductivity type;
etching the substrate through the trench pattern mask to form trenches in an area in the top of the substrate in the doped region;
forming a dielectric layer conformally over the top of the substrate including following the contour within the trenches;
forming a polysilicon layer over the dielectric layer to overfill the trenches;
forming a top metal layer over the polysilicon layer;
forming a top plate pattern mask over the top metal layer; and
etching the polysilicon and top metal layers through the top plate pattern mask to define a capacitor top plate, a capacitor bottom plate being defined by the trenched doped region of the semiconductor substrate;
wherein the doped region of given conductivity type comprises an upper region of the given conductivity type; and wherein the substrate further includes central and lower regions of the given conductivity type; the central region being located between the upper and lower regions, and having a doping concentration that is less than doping concentrations of the upper and lower regions.
2. The method of claim 1 , wherein the upper region has a thickness that is less than a depth of the trenches, and generally follows the contour of the trenches.
3. The method of claim 1 , further comprising forming a bottom metal layer over a bottom of the substrate in contact with the lower doping region.
4. A method for forming a semiconductor device including a capacitor, comprising:
forming a trench pattern mask over a top of a semiconductor substrate including a doped region of given conductivity type;
etching the substrate through the trench pattern mask to form trenches in an area in the top of the substrate in the doped region;
forming a dielectric layer conformally over the top of the substrate including following the contour within the trenches;
forming a polysilicon layer over the dielectric layer to overfill the trenches;
forming a top metal layer over the polysilicon layer;
forming a top plate pattern mask over the top metal layer; and
etching the polysilicon and top metal layers through the top plate pattern mask to define a capacitor top plate, a capacitor bottom plate being defined by the trenched doped region of the semiconductor substrate;
wherein the dielectric and polysilicon layers are formed with portions extending laterally beyond the trenched area; the method further comprises forming a hardmask layer over the polysilicon layer, forming a hardmask pattern mask over the hardmask layer, and etching the hardmask layer through the hardmask pattern mask to form a hardmask segment laterally separated from the trenched area; the top metal layer is formed over the polysilicon layer including over the hardmask segment; the top plate pattern mask includes a contact pattern; and the etching the polysilicon and top metal layers through the top plate pattern etches the top metal layer down to the hardmask layer and defines a top side contact separated from the capacitor top plate by a laterally extending resistor-defining portion of the polysilicon layer.
5. The method of claim 4 , further comprising doping the polysilicon layer to provide top side contact, resistor and capacitor top plate regions, with the resistor regions having a lesser doping concentration than the top side contact and capacitor top plate regions.