IP Library Granted Patent US 8,638,161
Granted Patent B2
US 8,638,161 · App. 13/187,302 · Granted Jan 28, 2014

Power control device and method therefor

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Quick Facts
Patent No.
US 8,638,161
App. No.
13/187,302
Granted
Jan 28, 2014
Kind
B2
Abstract

Power control is facilitated. In accordance with one or more embodiments, power is supplied to power rails of an integrated circuit using a power control circuit including a power regulator and a reset circuit that is responsive to a supply voltage. The power regulator provides power to the power rails, based upon a control signal. The reset circuit controls the power regulator to provide power to the power rails independently of the control signal when the supply voltage is below an operational voltage level, and controls the power regulator to provide power to the power rails in response to the control signal when the supply voltage reaches the operational voltage level.

Claims (50)

1. A power control circuit for powering power rails of an integrated circuit, the power control circuit comprising:

a power regulator configured and arranged to provide power to the power rails, based upon a control signal; and

a reset circuit configured and arranged to detect the supply voltage of power supplied to the power regulator and to,

in response to the detected supply voltage being below an operational voltage level, control the power regulator to provide power to the power rails independently of the control signal, and

in response to the detected supply voltage reaching the operational voltage level, output a reset signal to reset the control signal and, after resetting the control signal, control the power regulator to provide power to the power rails based on the control signal.

2. The power control circuit of claim 1 , wherein the reset circuit is configured and arranged to control the power regulator to operate independently of the control signal by outputting a signal that causes the power regulator to

ignore control signals that would regulate the power provided by the power regulator, and output unregulated power to the power rails.

3. The power control circuit of claim 1 , wherein

the power regulator includes a clamp circuit configured and arranged to couple received power at the regulator to the power rails, and

the reset circuit is configured and arranged to

control the power regulator to provide power to the power rails independently of the control signal by controlling the clamp circuit to couple the received power to the power rails, and,

control the power regulator to provide power to the power rails based on the control signal by controlling the clamp circuit to decouple the received power from the power rails.

4. The power control circuit of claim 1 , wherein

the reset circuit is configured and arranged to control the power regulator to operate independently of the control signal by outputting a reset signal to the power regulator, and

the power regulator is configured and arranged to operate independently of the control signal in response to the reset signal.

5. The power control circuit of claim 1 , wherein the reset circuit is configured and arranged to

control the power regulator to operate independently of the control signal by outputting a reset signal to the power regulator to control the power regulator to operate independently of the control signal, and

control the power regulator to respond to the control signal by stopping outputting the reset signal to control the power regulator to respond to the control signal.

6. The power control circuit of claim 1 , wherein the reset circuit is configured and arranged to control the power regulator to respond to the control signal in response to the control signal stabilizing and being reset.

7. The power control circuit of claim 1 , further including a second power regulator configured and arranged to power control circuitry that generates the control signal.

8. The power control circuit of claim 1 ,

further including a second regulator configured and arranged to power control circuitry that generates the control signal, and to output an ignore signal until the second regulator supplies power to the control circuitry at a threshold voltage level at which the control circuitry can stably generate the control signal; and

the power regulator is configured to respond to the ignore signal by ignoring the generated control signal.

9. The power control circuit of claim 1 , further including, for each of the power rails, a rail voltage detector configured and arranged to detect a rail voltage of the power rail, and to output a reset signal to a circuit powered via the power rail, in response to the power regulator outputting a voltage to the power rail that exceeds a predefined threshold voltage level at which the circuit powered via the power rail operates.

10. The power control circuit of claim 1 , further including, for each of the power rails, a rail voltage detector configured and arranged to detect a rail voltage of the power rail, and to output synchronized reset signals to reset all circuits powered via the power rail, in response to the power regulator outputting a voltage to the power rail that exceeds a predefined threshold voltage level at which the circuits powered via the power rail operate.

11. The power control circuit of claim 1 , wherein the power regulator includes control logic that generates the control signal, the control logic being powered by voltage that the power regulator regulates.

12. A power control circuit for powering power rails of an integrated circuit, the power control circuit comprising:

a first power regulator configured and arranged to provide power to a first power rail, based upon a control signal;

a control circuit configured and arranged to generate the control signal;

a second power regulator configured and arranged to power the control circuit and to provide power to a second power rail at a standby power level; and

a reset circuit configured and arranged to control the first power regulator to provide power to the first power rail independently of the control signal, in response to power supplied to the control circuit being less than a first predefined power level at which the control circuit operates.

13. The power control circuit of claim 12 , wherein the reset circuit is configured and arranged to control the first power regulator to provide power to the first power rail independently of the control signal in response to a supply voltage provided to the power control circuit being below a predefined voltage.

14. The power control circuit of claim 12 , wherein the reset circuit is configured and arranged to control the first power regulator to provide power to the first power rail independently of the control signal in response to a supply voltage provided to the control circuit by the second power regulator being below a predefined voltage.

15. The power control circuit of claim 12 , wherein

the second power regulator includes at least a portion of the reset circuit, and

the portion of the reset circuit is configured and arranged to generate an ignore output signal to control the first power regulator to provide power to the first power rail independently of the control signal in response to a startup condition, and to stop generating the ignore output in response to the second power regulator reaching a predefined voltage level.

16. The power control circuit of claim 12 , wherein the reset circuit is configured and arranged to detect the supply voltage of power supplied to the power regulator and to

in response to the detected supply voltage being below an operational voltage level, control the power regulator to provide power to the first power rail independently of the control signal, and

in response to the detected supply voltage reaching the operational voltage level, control the power regulator to provide power to the first power rail based on the control signal.

17. The power control circuit of claim 12 , wherein the second power regulator is further configured and arranged to power the control circuit and to provide power to a second power rail independent of the control signal.

18. The power control circuit of claim 12 , further comprising

a second reset circuit configured and arranged to control the second power regulator to provide power to the second power rail independently of the control signal, in response to power supplied to the control circuit being less than a second predefined power level, the second predefined power level being different than the first predefined power level.

19. A method for powering power rails of an integrated circuit, the method comprising:

providing a control signal to a power regulator circuit for controlling the power regulator circuit to provide power to the power rails;

in response to a supply power being below a threshold, controlling the power regulator circuit to provide power to the power rails independently of the control signal; and

in response to the supply power reaching the threshold, controlling the power regulator circuit to provide power to the power rails based on the control signal,

wherein providing a control signal to a power regulator circuit includes generating the control signal at a control circuit,

further including powering the control circuit with a standby power regulator circuit, and

wherein controlling the power regulator circuit to provide power to the power rails independently of the control signal in response to a supply power being below a threshold includes controlling the power regulator to provide the power to the power rails independently of the control signal in response to a voltage level of the standby power regulator being below a threshold, and

wherein controlling, in response to the supply power reaching the threshold, the power regulator circuit to provide power to the power rails based on the control signal includes controlling the power regulator to provide the power to the power rails in response to the supply voltage level of the standby power regulator reaching the threshold.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 042521/0706 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SIGNATURE PAGE PREVIOUSLY RECORDED AT REEL: 039490 FRAME: 0688. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Sep 13, 2016
From: NXP B.V.
To: VLSI TECHNOLOGY LLC
Reel/Frame 040022/0638 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2016
From: NXP B.V.
To: VLSI TECHNOLOGY LLC
Reel/Frame 039490/0688 →
PATENT RELEASE Recorded Jul 22, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS GLOBAL COLLATERAL AGENT; MORGAN STANLEY SENIOR FUNDING, INC., AS RCF ADMINISTRATIVE AGENT; MORGAN STANLEY SENIOR FUNDING, INC., AS THE NOTES COLLATERAL AGENT
To: NXP B.V.
Reel/Frame 039428/0845 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2012
From: ROBERTSON, PETER; GUNTHER, ANDRE; MAHOOTI, KEVIN
To: NXP B.V.
Reel/Frame 028691/0387 →