Substrate structure for ejection chip and method for fabricating substrate structure

1. A substrate structure for an ejection chip, the substrate structure comprising:

a first substrate layer;

a second substrate layer disposed beneath the first substrate layer;

an intermediate layer configured between the first substrate layer and the second substrate layer, wherein the intermediate layer is an insulating layer and the first substrate layer, second substrate layer, and intermediate layer together form a silicon-on-insulator structure;

a plurality of fluid channels configured within the second substrate layer;

a plurality of fluid ports configured within the first substrate layer, at least one fluid port of the plurality of fluid ports being configured in alignment with a corresponding fluid channel of the plurality of fluid channels; and

a plurality of slots configured within the intermediate layer such that the at least one fluid port of the plurality of fluid ports is in fluid communication with the corresponding fluid channel of the plurality of fluid channels.

2. The substrate structure of claim 1 , wherein the intermediate layer is composed of silicon oxide.

3. The substrate structure of claim 1 , wherein the first substrate layer has a thickness ranging from about 10 microns (μm) to about 80 μm.

4. The substrate structure of claim 1 , wherein the second substrate layer has a thickness ranging from about 100 μm to about 800 μm.

5. The substrate structure of claim 1 , wherein the intermediate layer has a thickness ranging from about 0.5 μm to about 5 μm.

6. The ejection chip of claim 1 , further including a sacrificial layer in the fluid ports for uniform coating before flow feature patterning.

7. An ejection chip for an inkjet printer, the ejection chip comprising:

a substrate structure comprising,

a first substrate layer,

a second substrate layer disposed beneath the first substrate layer,

an intermediate layer configured between the first substrate layer and the second substrate layer, wherein the intermediate layer is an insulating layer and the first substrate layer, second substrate layer, and intermediate layer together form a silicon-on-insulator structure,

a plurality of fluid channels configured within the second substrate layer,

a plurality of fluid ports configured within the first substrate layer, at least one fluid port of the plurality of fluid ports being configured in alignment with a corresponding fluid channel of the plurality of fluid channels, and

a plurality of slots configured within the intermediate layer such that the at least one fluid port of the plurality of fluid ports is in fluid communication with the corresponding fluid channel of the plurality of fluid channels;

at least one fluid ejection element carried by the substrate structure and adapted to eject a fluid therefrom;

a flow feature layer configured over the substrate structure, the flow feature layer comprising a plurality of flow features, each flow feature of the plurality of flow features being configured in fluid communication with at least one corresponding fluid port of the plurality of fluid ports of the first substrate layer; and

a nozzle plate configured over the flow feature layer, the nozzle plate comprising a plurality of nozzles, each nozzle of the plurality of nozzles being configured in fluid communication with at least one corresponding flow feature of the plurality of flow features of the flow feature layer.

8. The ejection chip of claim 7 , wherein the intermediate layer is composed of silicon oxide.