Manufacturing method and structure of non-volatile memory
View Patent ↗A non-volatile memory structure includes a substrate; a poly gate structure formed on the substrate; a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and an inter-layer dielectric layer formed on the first silicon oxide layer. The first silicon oxide layer has a density higher than that of the inter-layer dielectric layer.
1. A method for manufacturing a non-volatile memory, comprising:
providing a substrate formed thereon a poly gate structure;
forming a contact etching stop layer over the poly gate structure, which includes at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and
forming an inter-layer dielectric layer over the contact etching stop layer;
wherein the first silicon oxide layer is disposed adjacent to the inter-layer dielectric layer and has a density higher than that of the inter-layer dielectric layer.
2. The method according to claim 1 , wherein the poly gate structure includes at least one polysilicon conductor.
3. The method according to claim 2 , wherein the poly gate structure is formed by:
forming a dielectric layer on the substrate;
forming the polysilicon conductor on the dielectric layer;
forming a sidewall structure around the polysilicon conductor; and
forming a metal silicide on the polysilicon conductor.
4. The method according to claim 1 , wherein the contact etching stop layer is formed by:
forming a second silicon oxide layer over the poly gate structure;
forming the silicon nitride layer on the second silicon oxide layer; and
forming the first silicon oxide layer on the silicon nitride layer.
5. The method according to claim 1 , wherein the first silicon oxide layer is formed of tetraethyl orthosilicate by plasma enhanced chemical vapor deposition to a thickness ranged between 300 and 2000 angstroms.
6. The method according to claim 1 , wherein the inter-layer dielectric layer is formed by atmospheric pressure chemical vapor deposition.
7. A non-volatile memory structure, comprising:
a substrate;
a poly gate structure formed on the substrate;
a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and
an inter-layer dielectric layer formed on the first silicon oxide layer;
wherein the first silicon oxide layer has a density higher than that of the inter-layer dielectric layer.
8. The non-volatile memory structure according to claim 7 , wherein the poly gate structure includes at least one polysilicon conductor configured to form a floating gate of the non-volatile memory.
9. The non-volatile memory structure according to claim 8 , wherein the poly gate structure further includes:
a dielectric layer disposed between the substrate and the polysilicon conductor;
a sidewall structure disposed around the polysilicon conductor; and
a metal silicide layer disposed on the polysilicon conductor.
10. The non-volatile memory structure according to claim 7 , wherein the contact etching stop layer further includes a second silicon oxide layer disposed between the poly gate structure and the silicon nitride layer.
11. The non-volatile memory structure according to claim 7 , wherein the first silicon oxide layer is a compressive strain layer having a thickness ranged between 300 and 2000 angstroms.
12. The non-volatile memory structure according to claim 7 , wherein the inter-layer dielectric layer is formed of silicon oxide.