Gate control circuit
An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.
1. An integrated circuit for switching a transistor, comprising:
an operational amplifier configured to switch the transistor;
slew rate control circuitry configured to control slew rate during switching of the transistor; and
discharge control circuitry configured to provide a discharge path when the transistor is switched off.
2. The integrated circuit of claim 1 , wherein the operational amplifier is configured to switch the transistor in response to an input signal.
3. The integrated circuit of claim 1 , further comprising delay control circuitry configured to set a delay period and wherein the operational amplifier is configured to not begin switching the transistor until after expiration of the delay period.
4. The integrated circuit of claim 1 , further comprising a charge pump configured to generate a requisite gate drive voltage for the transistor.
5. The integrated circuit of claim 4 , further comprising circuitry to pre-charge a storage capacitor of the charge pump.
6. The integrated circuit of claim 1 , further comprising fault protection circuitry for detecting and protecting against one or more fault conditions.
7. The integrated circuit of claim 6 , wherein the fault protection circuitry includes one or more of: under voltage lock out circuitry, over current shut down circuitry, and over temperature shut down circuitry.
8. The integrated circuit of claim 1 , wherein an output of the operational amplifier is input into a latch and wherein an output of the latch is connected to the transistor gate.
9. The integrated circuit of claim 8 , wherein the latch is set when the transistor is fully turned on or fully turned off.
10. The integrated circuit of claim 8 , wherein a latched output of the operational amplifier holds a gate drive voltage of the transistor at an on voltage level or at an off voltage level and consumes no active power.
11. The integrated circuit of claim 1 , wherein the integrated circuit consumes active power while switching on or switching off the transistor but not during quiescent states of the transistor.
12. The integrated circuit of claim 1 , wherein the transistor comprises one of a plurality of transistors controlled by the integrated circuit.
13. The integrated circuit of claim 1 , wherein the integrated circuit outputs a signal that indicates when the transistor gate voltage has reached a steady state value.
14. The integrated circuit of claim 1 , wherein the integrated circuit is part of a series of integrated circuits daisy chained together to facilitate sequential switching of a series of associated power rails.
15. The integrated circuit of claim 1 , wherein the transistor is included in the integrated circuit.
16. The integrated circuit of claim 1 , wherein the integrated circuit includes circuitry to determine a current across the transistor.
17. The integrated circuit of claim 1 , wherein the transistor comprises a Field Effect Transistor (FET).
18. The integrated circuit of claim 1 , wherein the transistor comprises a power rail switch.
19. The integrated circuit of claim 1 , wherein the integrated circuit comprises a gate driver of the transistor.
20. A method for switching a transistor, comprising:
configuring an operational amplifier to switch the transistor;
configuring slew rate control circuitry to control slew rate during switching of the transistor; and
configuring discharge control circuitry to provide a discharge path when the transistor is switched off.