Semiconductor device
View Patent ↗A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.
1. A device comprising:
a substrate including first and second surfaces;
a semiconductor chip including third and fourth surfaces, the third surface facing toward the first surface;
first and second pads provided above the third surface of the semiconductor chip, the first and second pads being connected to each other through a first wire connected on top surfaces of the first and second pads; and
a first wiring layer provided on the second surface of the substrate, the first wiring layer being connected to the first pad and the second pad being connected to the first wiring layer through the first pad.
2. The device according to claim 1 , wherein the substrate includes a penetrating opening, the first and second pads are positioned in the penetrating opening in plan view.
3. The device according to claim 2 , further comprising:
a second wire coupling the first pad and the first wiring layer.
4. The device according to claim 3 , further comprising:
a first bonding pad provided on the second surface, the first bonding pad being coupled to the first wiring layer, the second wire being coupled through the penetrating opening to the first bonding pad, the first bonding pad being closer to the first pad than the second pad.
5. The device according to claim 4 , further comprising:
a plurality of pads including the first and second pads;
a plurality of bonding pads including the first bonding pad; and
a plurality of wiring layers including the first wiring layer, each of the plurality of wiring layers being provided with a corresponding one of the plurality of bonding pads,
wherein the number of the pads is greater than the number of the bonding pads and greater than the number of the wiring layers.
6. The semiconductor device according to claim 1 , further comprising:
a second wiring layer provided on the second surface; and
a third electrode pad provided on the third surface, the third electrode pad being coupled to the second wiring layer, the third electrode pad being positioned between the first and second electrode pads.
7. The device according to claim 1 , wherein the first and second pads are connected to each other by the first wire, the first wire having a first end part that is bonded about the first pad, and
wherein the first wiring layer is connected to the first pad by a second wire, the second wire having a second end part that is bonded above the first end part of the first wire.
8. A device comprising:
a substrate including a penetrating opening, the substrate including first and second surfaces;
a first semiconductor chip including third and fourth surfaces, the first semiconductor chip being mounted over the substrate so that the third surface faces toward the first surface;
first and second electrode pads provided on the third surface, the first and second electrode pads being positioned in the penetrating opening in plan view, the first and second electrode pads being configured to have the same electric potential;
a first wire coupling the first and second electrode pads, the first wire being connected over surfaces of the first and second electrode pads facing the penetrating opening;
a first wiring layer provided on the second surface; and
a second wire coupling the second electrode pad and the first wiring layer through the penetrating opening, the first electrode pad being coupled to the first wiring layer through the second electrode pad.
9. The semiconductor device according to claim 8 , further comprising:
a first bonding pad provided on the second surface, the second wire being coupled through the first bonding pad to the first wiring layer, the first bonding pad being farther from the first electrode pad than the second electrode pad.
10. The semiconductor device according to claim 9 , further comprising:
a sealant filling the penetrating opening, the sealant sealing the first and second electrode pads, the first bonding pad, and the first and second wires.
11. The semiconductor device according to claim 8 , further comprising:
a second semiconductor chip including fifth and sixth surfaces, the second semiconductor chip being stacked over the first semiconductor chip so that the sixth surface faces the fourth surface;
third and fourth electrode pads provided on the fifth surface, the third and fourth electrode pads being coupled to each other, the third and fourth electrode pads being configured to have the same electric potential; and
a second wiring layer provided on the first surface, the fourth electrode pad being coupled to the second wiring layer.
12. The semiconductor device according to claim 11 , further comprising:
a third wire coupling the third and fourth electrode pads; and
a fourth wire coupling the fourth electrode pad and the second wiring layer.
13. The semiconductor device according to claim 12 , further comprising:
a second bonding pad provided on the first surface, the fourth wire being coupled through the second bonding pad to the second wiring layer, the second bonding pad being farther from the third electrode pad than the fourth electrode pad.
14. The semiconductor device according to claim 8 , further comprising:
a third bonding pad provided on the second surface; and
a fifth electrode pad provided on the third surface, the fifth electrode pad being coupled to the third bonding pad, the fifth electrode pad being positioned between the first and second electrode pads.
15. The semiconductor device according to claim 8 , further comprising:
a sixth electrode pad provided between the first and second electrode pads, the sixth electrode pad being uncoupled to the first and second electrode pads.
16. The device according to claim 8 , wherein the first wire has a first end part that is bonded about the second electrode pad, and
wherein the second wire has a second end part that is bonded above the first end part of the first wire.
17. A semiconductor device comprising:
a wiring board including a bonding pad thereon;
a semiconductor chip including first and second electrode pads thereon, the semiconductor chip being mounted over the wiring board so that the first and second electrode pads face the wiring board;
a first wire including a first end part of the first wire, the first end part of the first wire being bonded above the first electrode pad to electrically couple the first electrode pad and the second electrode pad, the first and second electrode pads being connected to each other through the first wire connected on top surfaces of the first and second pads; and
a second wire including a second end part of the second wire, the second wire being bonded above the first end part of the first wire to electrically couple the first electrode pad and the bonding pad.
18. The semiconductor device according to claim 17 , further comprising:
a bump provided on the first electrode pad of the semiconductor chip, the first end part of the first wire being bonded above the first electrode pad via the bump.
19. The semiconductor device according to claim 17 , wherein the first electrode pad is positioned near the bonding pad than the second electrode pad.
20. The semiconductor device according to claim 17 , wherein the second electrode pad is positioned near the first electrode pad than the bonding pad, and
the first wire is shorter than the second wire.