Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
A die stack having a second die is stacked vertically on top of a first die. A first plurality of test pads is located along a first edge of the first die. A second plurality of test pads is located along a second edge of the first die. The first edge of the first die is parallel to the second edge of the first die. A third plurality of test pads is located along a first edge of the second die. A fourth plurality of test pads is located along a second edge of the second die. The first edge of the second die is parallel to the second edge of the second die. The first edge of the first die and the second edge of the first die are perpendicular to the first edge of the second die and the second edge of the second die.
1. A system comprising:
a die stack, wherein the die stack comprises at least:
a first die;
a second die, wherein the second die is stacked vertically on top of the first die,
one or more redistribution layer (RDL);
one or more Though Silicon Via (TSV);
a first plurality of pads, wherein
the first plurality of pads is located along a first edge of the first die;
a second plurality of pads, wherein
the second plurality of pads is located along a second edge of the first die, and
the first edge of the first die is parallel to the second edge of the first die;
a third plurality of pads, wherein
the third plurality of pads is located along a first edge of the second die;
a fourth plurality of pads, wherein
the fourth plurality of pads is located along a second edge of the second die,
the first edge of the second die is parallel to the second edge of the second die, and
the first edge of the first die and the second edge of the first die are perpendicular to the first edge of the second die and the second edge of the second die; and
one or more Serializer/Deserializer (Ser/Des) circuit blocks, wherein
at least one die of said die stack comprises said one or more Ser/Des circuit blocks,
the first plurality of pads are a first plurality of test pads,
the second plurality of pads are a second plurality of test pads,
the third plurality of pads are a third plurality of test pads, and
the fourth plurality of pads are a fourth plurality of test pads.
2. The system according to claim 1 , wherein
said one or more said redistribution layer provide at least one physical connection among said one or more Though Silicon Via on two adjacent dies of said die stack.
3. The system according to claim 1 , wherein
said one or more Though Silicon Via from each die of said die stack are aligned on the top of each other.
4. The system according to claim 1 , wherein
said one or more Though Silicon Via is used within the one or more Ser/Des circuit blocks.
5. The system according to claim 1 , wherein
said die stack is mounted on top of a substrate.