IP Library Granted Patent US 8,779,853
Granted Patent B2
US 8,779,853 · App. 13/192,301 · Granted Jul 15, 2014

Amplifier with multiple zero-pole pairs

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,779,853
App. No.
13/192,301
Granted
Jul 15, 2014
Kind
B2
Abstract

An amplifier is disclosed. In accordance with some embodiments of the present disclosure, an amplifier may comprise a differential pair comprising a first transistor and a second transistor, wherein the first transistor comprises a first portion and a second portion, a first compensation circuit comprising a first terminal coupled to the first portion of the first transistor and a second terminal coupled to the second transistor, and a second compensation circuit comprising a first terminal coupled to the second portion of the first transistor and a second terminal coupled to the second transistor and the second terminal of the first compensation circuit.

Claims (88)

1. An amplifier, comprising:

a differential pair comprising a first transistor and a second transistor, wherein the first transistor comprises a first portion and a second portion;

a first compensation circuit comprising:

a first terminal coupled to the first portion of the first transistor; and

a second terminal coupled to the second transistor; and

a second compensation circuit comprising:

a first terminal coupled to the second portion of the first transistor; and

a second terminal coupled to the second transistor and the second terminal of the first compensation circuit.

2. The amplifier of claim 1 , wherein:

the first compensation circuit comprises a first resistor and a first capacitor; and

the second compensation circuit comprises a second resistor and a second capacitor.

3. The amplifier of claim 2 , wherein:

a first terminal of the first resistor and a first terminal of the first capacitor are coupled together at the first terminal of the first compensation circuit;

a second terminal of the first resistor and a second terminal of the first capacitor are coupled together at the second terminal of first compensation circuit;

a first terminal of the second resistor and a first terminal of the second capacitor are coupled together at the first terminal of the second compensation circuit; and

a second terminal of the second resistor and a second terminal of the second capacitor are coupled together at the second terminal of second compensation circuit.

4. The amplifier of claim 1 , wherein:

the first transistor comprises a first N-type metal-oxide semiconductor field-effect transistor (NMOS);

a gate of the first portion of the first NMOS is coupled to a gate of the second portion of the first NMOS;

a drain of the first portion of the first NMOS is coupled to a drain of the second portion of the first NMOS;

a source of the first portion of the first NMOS is coupled to the first terminal of the first compensation circuit;

a source of the second portion of the first NMOS is coupled to the first terminal of the second compensation circuit;

the second transistor comprises a second NMOS; and

a source of the second NMOS is coupled to the second terminal of the first compensation circuit and the second terminal of the second compensation circuit.

5. The amplifier of claim 1 , wherein the size of the first portion of the first transistor is equivalent to the size of the second portion of the first transistor.

6. The amplifier of claim 1 , wherein the size of the second transistor is equivalent to the combined size of the first portion of the first transistor and the second portion of the first transistor.

7. An amplifier comprising, comprising:

a first stage comprising:

a differential pair comprising a first transistor and a second transistor, wherein the first transistor comprises a first portion and a second portion;

a first compensation circuit comprising:

a first terminal coupled to the first portion of the first transistor; and

a second terminal coupled to the second transistor; and

a second compensation circuit comprising:

a first terminal coupled to the second portion of the first transistor; and

a second terminal coupled to the second transistor and the second terminal of the first compensation circuit; and

a second stage comprising a source-follower transistor comprising a metal-oxide semiconductor field-effect transistor (MOSFET) comprising a gate coupled to a first-stage output and source coupled to an amplifier output.

8. The amplifier of claim 7 , wherein:

the first compensation circuit comprises a first resistor and a first capacitor; and

the second compensation circuit comprises a second resistor and a second capacitor.

9. The amplifier of claim 8 , wherein:

a first terminal of the first resistor and a first terminal of the first capacitor are coupled together at the first terminal of the first compensation circuit;

a second terminal of the first resistor and a second terminal of the first capacitor are coupled together at the second terminal of first compensation circuit;

a first terminal of the second resistor and a first terminal of the second capacitor are coupled together at the first terminal of the second compensation circuit; and

a second terminal of the second resistor and a second terminal of the second capacitor are coupled together at the second terminal of second compensation circuit.

10. The amplifier of claim 7 , wherein:

the first transistor comprises a first N-type metal-oxide semiconductor field-effect transistor (NMOS);

a gate of the first portion of the first NMOS is coupled to a gate of the second portion of the first NMOS;

a drain of the first portion of the first NMOS is coupled to a drain of the second portion of the first NMOS;

a source of the first portion of the first NMOS is coupled to the first terminal of the first compensation circuit;

a source of the second portion of the first NMOS is coupled to the first terminal of the second compensation circuit;

the second transistor comprises a second NMOS; and

a source of the second NMOS is coupled to the second terminal of the first compensation circuit and the second terminal of the second compensation circuit.

11. The amplifier of claim 7 , wherein the size of the first portion of the first transistor is equivalent to the size of the second portion of the first transistor.

12. The amplifier of claim 7 , wherein the size of the second transistor is equivalent to the combined size of the first portion of the first transistor and the second portion of the first transistor.

13. A voltage regulator, comprising:

a voltage reference generator;

an amplifier comprising:

a first stage comprising:

a differential pair comprising a first transistor and a second transistor, wherein the first transistor comprises a first portion and a second portion;

a first compensation circuit comprising:

a first terminal coupled to the first portion of the first transistor; and

a second terminal coupled to the second transistor; and

a second compensation circuit comprising:

a first terminal coupled to the second portion of the first transistor; and

a second terminal coupled to the second transistor and the second terminal of the first compensation circuit; and

a second stage comprising a source-follower transistor comprising a metal-oxide semiconductor field-effect transistor (MOSFET) comprising a gate coupled to a first-stage output and source coupled to an amplifier output;

an output transistor; and

a feedback network.

14. The voltage regulator of claim 13 , wherein:

the first compensation circuit comprises a first resistor and a first capacitor; and

the second compensation circuit comprises a second resistor and a second capacitor.

15. The voltage regulator of claim 14 , wherein:

a first terminal of the first resistor and a first terminal of the first capacitor are coupled together at the first terminal of the first compensation circuit;

a second terminal of the first resistor and a second terminal of the first capacitor are coupled together at the second terminal of first compensation circuit;

a first terminal of the second resistor and a first terminal of the second capacitor are coupled together at the first terminal of the second compensation circuit; and

a second terminal of the second resistor and a second terminal of the second capacitor are coupled together at the second terminal of second compensation circuit.

16. The voltage regulator of claim 13 , wherein:

the first transistor comprises a first N-type metal-oxide semiconductor field-effect transistor (NMOS);

a gate of the first portion of the first NMOS is coupled to a gate of the second portion of the first NMOS;

a drain of the first portion of the first NMOS is coupled to a drain of the second portion of the first NMOS;

a source of the first portion of the first NMOS is coupled to the first terminal of the first compensation circuit;

a source of the second portion of the first NMOS is coupled to the first terminal of the second compensation circuit;

the second transistor comprises a second NMOS; and

a source of the second NMOS is coupled to the second terminal of the first compensation circuit and the second terminal of the second compensation circuit.

17. The voltage regulator of claim 13 , wherein the size of the first portion of the first transistor is equivalent to the size of the second portion of the first transistor.

18. The voltage regulator of claim 13 , wherein the size of the second transistor is equivalent to the combined size of the first portion of the first transistor and the second portion of the first transistor.

19. The voltage regulator of claim 13 , wherein the output transistor comprises a MOSFET comprising a gate coupled to the amplifier output and a source coupled to a voltage regulator output.

20. The voltage regulator of claim 13 , wherein the reference generator comprises a bandgap reference.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056524/0373 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
To: INTEL IP CORPORATION
Reel/Frame 031105/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
Reel/Frame 030793/0586 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2011
From: ZHONG, KAI; YU, JOHN
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 026660/0487 →