High-density nonvolatile memory and methods of making the same
View Patent ↗Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.
1. A method to form a nonvolatile memory cell, the method comprising:
i) forming a first conductor at a first height above a substrate;
ii) forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type;
iii) forming a first antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and
iv) forming a second conductor above the first antifuse.
2. The method of claim 1 , wherein forming the first semiconductor element comprises:
after forming the first conductor, depositing a semiconductor layer stack on the first conductor; and
patterning and etching the semiconductor layer stack to form the first pillar-shaped semiconductor element.
3. The method of claim 2 , wherein depositing the semiconductor layer stack comprises depositing polycrystalline silicon.
4. The method of claim 1 , wherein the substrate comprises monocrystalline silicon.
5. The method of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
6. The method of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
7. The method of claim 1 , wherein the third heavily doped layer is doped by ion implantation.
8. The method of claim 1 , wherein the first heavily doped layer is doped by in situ doping.
9. The method of claim 1 , wherein forming the first conductor comprises:
depositing a first tungsten layer; and
patterning and etching the first tungsten layer to form the first conductor.
10. The method of claim 1 , wherein the first antifuse comprises an oxide layer.
11. The method of claim 10 , wherein the oxide layer comprises silicon dioxide.