IP Library › Granted Patent US 8,765,603
Granted Patent B2
US 8,765,603 · App. 13/195,554 · Granted Jul 1, 2014

Method of forming a buffer layer

Inventors: Cheng-Hao Hou (Hsinchu, TW); Wei-Yang Lee (Taipei, TW); Xiong-Fei Yu (Hsinchu, TW); Kuang-Yuan Hsu (Fongyuan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,765,603
App. No.
13/195,554
Granted
Jul 1, 2014
Kind
B2
Abstract

Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.

Claims (36)

1. A method of forming a barrier layer for a semiconductor device comprising:

forming a high-k dielectric layer over a substrate;

forming a titanium nitride layer over the high-k dielectric layer;

forming a silicon layer on the titanium nitride layer;

annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer; and

forming an n-metal over the high-k dielectric layer.

2. The method of claim 1 , wherein forming the silicon layer comprises forming the silicon layer to a thickness of from 5 Å to 10 Å.

3. The method of claim 1 , wherein forming the silicon layer comprises forming the silicon layer to a thickness of from 50 Å to 1000 Å.

4. The method of claim 1 , further comprising removing a portion of the silicon layer not annealed into the titanium nitride layer, after the step of the annealing the silicon layer into the titanium nitride layer.

5. The method of claim 4 , further comprising removing the portion of the silicon layer using a wet etch solution comprising dilute hydrofluoric acid and ammonium hydroxide.

6. The method of claim 1 , further comprising thinning the annealed silicon layer prior to forming the n-metal.

7. The method of claim 6 , further comprising thinning the annealed silicon layer using a wet etch solution comprising dilute hydrofluoric acid and hydrogen peroxide.

8. The method of claim 4 , further comprising thinning the annealed silicon layer prior to forming the n-metal.

9. The method of claim 8 , further comprising thinning the annealed silicon layer using a wet etch solution comprising dilute hydrofluoric acid and hydrogen peroxide.

10. The method of claim 1 , further comprising forming a second layer of titanium nitride on the annealed silicon layer prior to forming the n-metal.

11. The method of claim 5 , further comprising forming a second layer of titanium nitride on the annealed silicon layer prior to forming the n-metal.

12. The method of claim 1 , the silicon layer being formed by at least one of a chemical vapor deposition process or a physical vapor deposition process.

13. The method of claim 1 , wherein the n-metal layer comprises aluminum.

14. A method of forming a semiconductor device comprising:

forming, in a substrate, a gate region and a source region with a channel region therebetween;

forming a high-k dielectric layer over the channel region;

forming a titanium nitride layer over the high-k dielectric layer;

forming a silicon layer on the titanium nitride layer;

annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer; and

forming an n-metal over the high-k dielectric layer.

15. The method of claim 14 , further comprising removing a portion of the silicon layer not annealed into the titanium nitride layer, after the annealing the silicon layer into the titanium nitride layer.

16. The method of claim 14 , wherein the n-metal layer comprises aluminum.

17. A method of forming a barrier layer for a semiconductor device comprising:

forming a gate dielectric layer over a substrate;

forming a cap barrier layer over the gate dielectric layer;

forming a silicon layer on the cap barrier layer;

annealing the silicon layer into the cap barrier layer to form an annealed silicon layer; and

forming an n-metal over the annealed silicon layer.

18. The method of claim 17 , wherein annealing the silicon layer comprises consuming an entirety of the silicon layer during the annealing step.

19. The method of claim 17 , wherein annealing the silicon layer comprises annealing the silicon layer at a temperature ranging from 400° C. to 1200° C. for a duration of 10 minutes to 30 minutes.

20. The method of claim 17 , further comprising forming an additional cap barrier layer over the annealed silicon layer, wherein the additional cap barrier layer is between the annealed silicon layer and the n-metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2011
From: HOU, CHENG-HAO; LEE, WEI-YANG; YU, XIONG-FEI; HSU, KUANG-YUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 026681/0915 →
Continuity (1)
Related Publication 20130032900A1 · Feb 7, 2013