IP Library Granted Patent US 8,489,973
Granted Patent B1
US 8,489,973 · App. 13/196,729 · Granted Jul 16, 2013

Numerical solution on LLR exchange in turbo equalization

Inventors: Lingqi Zeng (Turlock, CA); Yu Kou (San Jose, CA)
Assignee: SK hynix memory solutions inc.
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Quick Facts
Patent No.
US 8,489,973
App. No.
13/196,729
Granted
Jul 16, 2013
Kind
B1
Abstract

The present application refers to a method for determining an extrinsic information input to an ECC decoder of a turbo equalizer. In one embodiment, a first loop-back signal is represented with a first number of bits, wherein the first loop-back signal comprises a signal looped back from an output of an ECC decoder. An output of a signal detector is represented with a second number of bits. An extrinsic information input to the ECC decoder is determined based at least in part on the first loop-back signal, the represented output of the signal detector, and at least one comparison with at least one predetermined threshold.

Claims (68)

1. A method for determining an extrinsic information input to an error correction code (ECC) decoder of a turbo equalizer, comprising:

representing a first loop-back signal with a first number of bits, wherein the first loop-back signal comprises a signal looped back from an output of an ECC decoder;

determining by a limiter a limited loop-back signal by limiting a magnitude of the first loop-back signal to a predetermined threshold; and

determining an extrinsic information input to the ECC decoder based at least in part on the limited loop-back signal and an output of a signal detector.

2. The method of claim 1 , wherein determining the extrinsic information input comprises subtracting the limited loop-back signal from the output of the signal detector.

3. The method of claim 1 , wherein the predetermined threshold is a fraction of a saturated value for the first loop-back signal represented with the first number of bits.

4. The method of claim 3 , wherein the saturated value is a maximum magnitude that can be represented with the first number of bits.

5. The method of claim 1 , wherein a second loop-back signal is fed as an input into the signal detector, and wherein the second loop-back signal comprises a signal looped back from the output of the ECC decoder.

6. The method of claim 1 , wherein equalized samples are fed as input into the signal detector.

7. The method of claim 1 , wherein the signal detector comprises a soft-input soft-output (SISO) equalizer.

8. The method of claim 1 , wherein the ECC decoder comprises an LDPC decoder.

9. The method of claim 1 , wherein the extrinsic information input comprises a log-likelihood ratio (LLR).

10. A system for determining an extrinsic information input to an error correction code (ECC) decoder of a turbo equalizer, comprising:

a signal detector; and

an ECC decoder; and

wherein the system is configured to:

represent a first loop-back signal with a first number of bits, wherein the first loop-back signal comprises a signal looped back from an output of the ECC decoder;

determine a limited loop-back signal by limiting a magnitude of the first loop-back signal to a predetermined threshold; and

determine an extrinsic information input to the ECC decoder based at least in part on the limited loop-back signal and an output of a signal detector.

11. The system of claim 10 , wherein determining the extrinsic information input comprises subtracting the limited loop-back signal from the output of the signal detector.

12. The system of claim 10 , wherein the predetermined threshold is a fraction of a saturated value for the first loop-back signal represented with the first number of bits.

13. The system of claim 12 , wherein the saturated value is a maximum magnitude that can be represented with the first number of bits.

14. The system of claim 10 , wherein a second loop-back signal is fed as an input into the signal detector, and wherein the second loop-back signal comprises a signal looped back from the output of the ECC decoder.

15. The system of claim 10 , wherein equalized samples are fed as input into the signal detector.

16. The system of claim 10 , wherein the signal detector comprises a soft-input soft-output (SISO) equalizer.

17. The system of claim 10 , wherein the ECC decoder comprises an LDPC decoder.

18. The system of claim 10 , wherein the extrinsic information input comprises a log-likelihood ratio (LLR).

19. A method for determining an extrinsic information input to an error correction code (ECC) decoder of a turbo equalizer, comprising:

representing a first loop-back signal with a first number of bits, wherein the first loop-back signal comprises a signal looped back from an output of an ECC decoder;

representing an output of a signal detector with a second number of bits; and

determining using an extrinsic information block an extrinsic information input to the ECC decoder based at least in part on the first loop-back signal, the represented output of the signal detector, and at least one comparison with at least one predetermined threshold.

20. The method of claim 19 , wherein determining comprises:

in the event that a first condition is met, determining the extrinsic information input as a first positive predetermined threshold, wherein the first condition is met if the first loop-back signal exceeds a second positive predetermined threshold and further if the represented output of the signal detector is positively saturated;

in the event that a second condition is met, determining the extrinsic information input as a first negative predetermined threshold, wherein the second condition is met if the first loop-back signal is less than a second negative predetermined threshold and further if the represented output of the signal detector is negatively saturated; and

in the event that the first condition and the second condition are not met, determining the extrinsic information input, wherein determining comprises subtracting the first loop-back signal from the output of the signal detector.

21. The method of claim 20 , wherein a magnitude of the first positive predetermined threshold is the same as a magnitude of the first negative predetermined threshold.

22. The method of claim 20 , wherein a magnitude of the second positive predetermined threshold is the same as a magnitude of the second negative predetermined threshold.

23. The method of claim 20 , wherein a magnitude of the first positive predetermined threshold is a fraction of a saturated value for the extrinsic information input represented with a third number of bits.

24. The method of claim 23 , wherein the saturated value is a maximum magnitude that can be represented with the third number of bits.

25. The method of claim 20 , wherein a magnitude of the second positive predetermined threshold is a fraction of a saturated value for the first loop-back signal represented with the first number of bits.

26. The method of claim 25 , wherein the saturated value is a maximum magnitude that can be represented with the first number of bits.

27. The method of claim 19 , wherein a second loop-back signal is fed as an input into the signal detector, and wherein the second loop-back signal comprises a signal looped backed from the output of the ECC decoder.

28. The method of claim 19 , wherein equalized samples are fed as input into the signal detector.

29. The method of claim 19 , wherein the signal detector comprises a soft-input soft-output (SISO) equalizer.

30. The method of claim 19 , wherein the ECC decoder comprises an LDPC decoder.

31. The method of claim 19 , wherein the extrinsic information input comprises a log-likelihood ratio (LLR).

32. A system for determining an extrinsic information input to an error correction code (ECC) decoder of a turbo equalizer, comprising:

a signal detector; and

an ECC decoder; and

wherein the system is configured to:

represent a first loop-back signal with a first number of bits, wherein the first loop-back signal comprises a signal looped back from an output of the ECC decoder;

represent an output of the signal detector with a second number of bits; and

determine an extrinsic information input to the ECC decoder based at least in part on the first loop-back signal, the represented output of the signal detector, and at least one comparison with at least one predetermined threshold.

33. The system of claim 32 , wherein determining comprises:

in the event that a first condition is met, determining the extrinsic information input as a first positive predetermined threshold, wherein the first condition is met if the first loop-back signal exceeds a second positive predetermined threshold and further if the represented output of the signal detector is positively saturated;

in the event that a second condition is met, determining the extrinsic information input as a first negative predetermined threshold, wherein the second condition is met if the first loop-back signal is less than a second negative predetermined threshold and further if the represented output of the signal detector is negatively saturated; and

in the event that the first condition and the second condition are not met, determining the extrinsic information input, wherein determining comprises subtracting the first loop-back signal from the output of the signal detector.

34. The system of claim 33 , wherein a magnitude of the first positive predetermined threshold is the same as a magnitude of the first negative predetermined threshold.

35. The system of claim 33 , wherein a magnitude of the second positive predetermined threshold is the same as a magnitude of the second negative predetermined threshold.

36. The system of claim 33 , wherein a magnitude of the first positive predetermined threshold is a fraction of a saturated value for the extrinsic information input represented with a third number of bits.

37. The system of claim 36 , wherein the saturated value is a maximum magnitude that can be represented with the third number of bits.

38. The system of claim 33 , wherein a magnitude of the second positive predetermined threshold is a fraction of a saturated value for the first loop-back signal represented with the first number of bits.

39. The system of claim 38 , wherein the saturated value is a maximum magnitude that can be represented with the first number of bits.

40. The system of claim 32 , wherein a second loop-back signal is fed as an input into the signal detector, and wherein the second loop-back signal comprises a signal looped backed from the output of the ECC decoder.

41. The system of claim 32 , wherein equalized samples are fed as input into the signal detector.

42. The system of claim 32 , wherein the signal detector comprises a soft-input soft-output (SISO) equalizer.

43. The system of claim 32 , wherein the ECC decoder comprises an LDPC decoder.

44. The system of claim 32 , wherein the extrinsic information input comprises a log-likelihood ratio (LLR).

Assignments (2)
CHANGE OF NAME Recorded Feb 25, 2013
From: LINK_A_MEDIA DEVICES CORPORATION
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 029872/0455 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2011
From: ZENG, LINGQI; KOU, YU
To: LINK_A_MEDIA DEVICES CORPORATION
Reel/Frame 027073/0810 →
Continuity (1)
Provisional Application 61400826 · Aug 2, 2010