Trench device structure and fabrication
View Patent ↗A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer.
1. A vertical-current-flow device, comprising:
a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material;
a glass layer containing a dopant above said insulated gate;
permanent charge that forms an inversion layer at the semiconductor surface adjacent to said glass layer;
a doped polysilicon layer above said glass layer;
source and body diffusions of opposite conductivity types adjacent a sidewall of said trench;
a drift region positioned to receive majority carriers which have been injected by said source, and which have passed through said body diffusion; and
a drain region positioned to receive majority carriers which have passed through said drift region;
wherein said gate is capacitively coupled to control inversion of a portion of said body region.
2. The vertical-current-flow device of claim 1 , wherein said majority carriers are electrons.
3. A vertical-current-flow device, comprising:
a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material;
a glass layer containing a dopant above said insulated gate;
permanent charge that forms an inversion layer at the semiconductor surface adjacent to said glass layer;
a doped polysilicone layer above said glass layer;
source and body diffusions of opposite conductivity types adjacent a sidewall of said trench;
a drift region positioned to receive majority carriers which have been injected by said source, and which have passed through said body diffusion; and
a drain region positioned to receive majority carriers which have passed through said drift region;
wherein said gate is capacitively coupled to control inversion of a portion of said body region;
further comprising a lightly doped diffusion between said source diffusion and said body diffusion.
4. The device of claim 1 , wherein said dopant is a n-type dopant.
5. The device of claim 1 , wherein said dopant is a p-type dopant.
6. The device of claim 4 , wherein said n-type dopant is phosphorus, arsenic or antimony.
7. The device of claim 5 , wherein said p-type dopant is boron.
8. A high-density vertical power device, comprising:
at least one active device area;
at least one buried gate electrode, in a patterned trench within said active device area, which is capacitively coupled to control vertical current flow through semiconductor material adjacent to at least part of said buried gate electrode, between a source which lies alongside said trench and a drain which lies below said trench; and
at least one buried source contact electrode, in said patterned trench above said gate electrode, which makes contact to said source;
permanent charge embedded in sidewalls of said patterned trench, between said buried gate electrode and said buried source contact electrode;
wherein said buried gate electrode and said buried source contact electrode have patterns which are identical within said active device areas, but differ elsewhere.
9. The high-density vertical power device of claim 8 , wherein said buried source contact electrode is entirely within said patterned trench.
10. The high-density vertical power device of claim 8 , further comprising a lightly doped diffusion between said source and said semiconductor material.