Semiconductor structure with galvanic isolation
Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die.
1. A galvanically-isolated semiconductor structure comprising:
a substrate structure having a bottom surface and a top surface, the top surface being completely non-conductive such that no conductive structure both lies above the top surface and touches a conductive region that touches and lies below the top surface;
a lower plate that touches the non-conductive top surface of the substrate structure, the lower plate being metal;
a dielectric layer that touches the lower plate and the non-conductive top surface of the substrate structure, the dielectric layer having a top surface;
a high-voltage upper plate that touches the top surface of the dielectric layer, the high-voltage upper plate being metal and lying directly vertically over a portion of the lower plate; and
a high-voltage pad that touches the top surface of the dielectric layer, the high-voltage pad being spaced apart from the high-voltage upper plate.
2. The galvanically-isolated semiconductor structure of claim 1 wherein the lower plate is electrically isolated from all other conductive structures.
3. The galvanically-isolated semiconductor structure of claim 1 and further comprising a high-voltage die connected to the high-voltage pad, the high-voltage die having a plurality of bond pads.
4. The galvanically-isolated semiconductor structure of claim 3 and further comprising a bonding wire that touches the high-voltage upper plate and a bond pad on the high-voltage die.
5. The galvanically-isolated semiconductor structure of claim 3 and further comprising a solder ball that touches a bond pad of the plurality of bond pads and the high-voltage upper plate.
6. The galvanically-isolated semiconductor structure of claim 1 and further comprising a low-voltage upper plate that touches the top surface of the dielectric layer, the low-voltage upper plate being metal, and being spaced apart from the high-voltage upper plate and the high-voltage pad.
7. The galvanically-isolated semiconductor structure of claim 6 and further comprising a low-voltage pad that touches the top surface of the dielectric layer, the low-voltage pad being metal and spaced apart from the high-voltage upper plate, the high-voltage pad, and the low-voltage plate.
8. The galvanically-isolated semiconductor structure of claim 7 wherein the low-voltage upper plate lies directly vertically over a portion of the lower plate.
9. The galvanically-isolated semiconductor structure of claim 8 and further comprising:
a high-voltage die connected to the high-voltage pad, the high-voltage die having a plurality of bond pads; and
a low-voltage die connected to the low-voltage pad, the low-voltage die having a plurality of bond pads.
10. The galvanically-isolated semiconductor structure of claim 9 and further comprising a bonding wire connected to the high-voltage upper plate and a bond pad on the high-voltage die, and a bonding wire connected to the low-voltage upper plate and a bond pad on the low-voltage die.
11. The galvanically-isolated semiconductor structure of claim 9 and further comprising:
a first solder ball that touches the high-voltage upper plate and a bond pad of the plurality of bond pads of the high-voltage die; and
a second solder ball that touches the low-voltage upper plate and a bond pad of the plurality of bond pads of the low-voltage die.
12. The galvanically-isolated semiconductor structure of claim 9 and further comprising a lead frame, the lead frame having a single die attach pad, the bottom surface of the substrate structure being physically connected to the single die attach pad.
13. The galvanically-isolated semiconductor structure of claim 7 and further comprising:
a lower structure that touches the non-conductive top surface of the substrate structure, and lies laterally adjacent to and spaced apart from the lower plate, the lower structure being metal;
a first via that extends through the dielectric layer to touch the lower plate and the high-voltage upper plate, the first via being metal; and
a second via that extends through the dielectric layer to touch the lower plate and the low-voltage upper plate, the second via being metal.
14. The galvanically-isolated semiconductor structure of claim 8 and further comprising a conductive via that extends through the dielectric layer to touch the lower plate and low-voltage upper plate.
15. The galvanically-isolated semiconductor structure of claim 14 and further comprising:
a high-voltage die connected to the high-voltage pad, the high-voltage die having a plurality of bond pads; and
a low-voltage die connected to the low-voltage pad, the low-voltage die having a plurality of bond pads.
16. The galvanically-isolated semiconductor structure of claim 15 and further comprising a bonding wire connected to the high-voltage upper plate and a bonding pad on the high-voltage die, and a bonding wire connected to the low-voltage upper plate and a bonding pad on the low-voltage die.
17. The galvanically-isolated semiconductor structure of claim 14 and further comprising a conductive via that extends through the dielectric layer to touch the lower plate and high-voltage upper plate.
18. The galvanically-isolated semiconductor structure of claim 17 and further comprising:
a high-voltage die connected to the high-voltage pad, the high-voltage die having a plurality of bonding pads; and
a low-voltage die connected to the low-voltage pad, the low-voltage die having a plurality of bonding pads.
19. A galvanically-isolated semiconductor structure comprising:
a substrate structure having a bottom surface and a top surface;
a lower plate that touches the top surface of the substrate structure, the lower plate being metal;
a dielectric layer that touches the lower plate and the top surface of the substrate structure, the dielectric layer having a top surface;
a high-voltage upper plate that touches the top surface of the dielectric layer, the high-voltage upper plate being metal and lying directly vertically over a portion of the lower plate;
a high-voltage pad that touches the top surface of the dielectric layer, the high-voltage pad being spaced apart from the high-voltage upper plate;
a high-voltage die connected to the high-voltage pad, the high-voltage die having a plurality of bonding pads; and
a bonding wire connected to the high-voltage upper plate and a bonding pad on the high-voltage die.
20. A method of forming a galvanically-isolated semiconductor structure comprising:
forming a lower plate to touch a top surface of a substrate structure, the lower plate being metal, the top surface being completely non-conductive such that no conductive structure both lies above the top surface and touches a conductive region that touches and lies below the top surface;
forming a dielectric layer to touch the lower plate and the non-conductive top surface of the substrate structure, the dielectric layer having a top surface;
forming a plurality of upper metal structures that touch the top surface of the dielectric layer, the plurality of upper metal structures including a high-voltage upper plate that lies directly vertically over a portion of the lower plate, and a high-voltage pad spaced apart from the high-voltage upper plate.