Semiconductor device and method for manufacturing
View Patent ↗A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.
1. A semiconductor device comprising:
a semiconductor substrate provided with trenches arranged in a matrix;
a shallow trench isolation (STI) region formed between the trenches that are disposed in a second direction on the semiconductor substrate and extending in a first direction that intersects with the second direction;
a charge storage layer formed inside the trench; and
word lines formed on side surfaces of the trench that oppose in the first direction, the word lines being separated from each other and extending in the second direction, wherein an upper surface of each of the word lines protrudes from an upper surface of the semiconductor substrate.
2. The semiconductor device according to claim 1 , wherein upper and lower widths of each of the word lines in the first direction are substantially the same.
3. The semiconductor device according to claim 1 , wherein a recessed portion is formed in the STI region between the trenches in the second direction under the word lines, and
the charge storage layer formed in the STI region is provided so as to be embedded in the recessed portion.
4. The semiconductor device according to claim 1 , wherein the trench includes a recessed portion that has a depth larger than a thickness of the charge storage layer in the STI region between two adjacent trenches in the second direction.
5. The semiconductor device according to claim 1 , further comprising a first diffusion region on a bottom surface of the trench in the semiconductor substrate.
6. The semiconductor device according to claim 5 , further comprising a second diffusion region formed on both upper sides of the trench in the semiconductor substrate.
7. A flash memory device, comprising:
input components;
output components; and
an array of memory cell components comprising:
a semiconductor substrate provided with trenches arranged in a matrix;
a shallow trench isolation (STI) region formed between the trenches that are disposed in a second direction on the semiconductor substrate and extending in a first direction that intersects with the second direction;
a charge storage layer formed inside the trench; and
word lines formed on side surfaces of the trench that oppose in the first direction, the word lines being separated from each other and extending in the second direction, wherein an upper surface of each of the word lines protrudes from an upper surface of the semiconductor substrate.
8. The flash memory device according to claim 7 , wherein upper and lower widths of each of the word lines in the first direction are substantially the same.
9. The flash memory device according to claim 7 , wherein a recessed portion is formed in the STI region between the trenches in the second direction under the word lines, and the charge storage layer is formed in the STI region and is provided so as to be embedded in the recessed portion.
10. The flash memory device according to claim 7 , wherein the trench includes a recessed portion that has a depth larger than a thickness of the charge storage layer in the STI region between two adjacent trenches in the second direction.
11. The flash memory device according to claim 7 , further comprising a first diffusion region on a bottom surface of the trench in the semiconductor substrate.